Digital Design Verification Engineer, Staff
Toronto, ONSur place
Qualcomm Canada ULC
4+ ansCandidates need a bachelor's degree in a science or engineering field with 4+ years of ASIC design or verification experience, or an equivalent master's or PhD with less experience. Strong SystemVerilog, UVM and scripting skills and proven leadership and communication are required.
Verilog, SystemVerilog, UVM, Python, Perl, C/C++
Firmware Engineer – SerDes PHY (all levels)
Toronto, ONSur place
Qualcomm Canada ULC
6+ ansCandidates need an engineering or computer science degree and 4 to 6+ years of software engineering experience, depending on degree level. They also need at least 3 years of programming experience in languages such as C, C++, Java or Python.
JTAG debuggers, git, Verilog, SystemVerilog