Staff Verification Engineer, Compute Subsystems
Markham, ONSur place
Qualcomm Canada ULC
4+ ansCandidates need a relevant engineering degree and several years of ASIC design or verification experience, with hands-on work in SystemVerilog assertions, formal verification tools, and UVM. Scripting skills in Python, Perl, Tcl, or shell and strong problem-solving and communication abilities are also required.
SystemVerilog, UVM, VC Formal, JasperGold, Questa Formal, Python