Senior SoC Design Engineer
Burnaby, BC86k–186k $/anTemps plein
MS
MCHP Semiconductor Canada ULC
3+ ansCandidates need a Bachelor's or Master's in electrical or computer engineering and 3 to 5 years of related experience, including RTL design in SystemVerilog and Verilog. Experience with ASIC design flows, synthesis, static timing analysis and PCI-Express is valued.
Synopsys Design Compiler, Cadence Incisive, Verilog, Perl, Python, Tcl