DFT Engineer, Principal
Toronto, ONQualcomm Canada ULC
8+ ansCandidates need 10+ years of SoC experience in RTL, DFT or front-end roles, and extensive use of Siemens, Synopsys and Cadence DFT tools. Strong Verilog, VHDL and SystemVerilog skills, knowledge of JTAG, iJTAG and BIST standards, and TCL or Python scripting are expected.
Siemens DFT tools, Cadence DFT tools, Verilog, VHDL, SystemVerilog, TCL
Firmware Engineer, Principal
Toronto, ONQualcomm Canada ULC
8+ ansCandidates need an engineering or computer science degree plus 8+ years of software engineering experience, or a master's with 7+ years. They also need 4+ years coding in C, C++, Java or Python, strong embedded firmware and lab debug skills, and team leadership experience.
Git, Python, RISC-V
DFT Engineer (Senior to Staff level)
Toronto, ONQualcomm Canada ULC
10+ ansCandidates need a bachelor's degree in an engineering or computer science field and 10+ years of SoC design experience in RTL, DFT or front-end work. They need strong knowledge of DFT tools, Verilog, VHDL and SystemVerilog, and standards such as JTAG, iJTAG and BIST.
Siemens DFT tools, Cadence DFT tools, Verilog, VHDL, SystemVerilog, TCL
Firmware Engineer, Staff
Toronto, ONQualcomm Canada ULC
6+ ansCandidates need a bachelor's, master's or PhD in a related field plus 4, 3 or 2 years of software engineering experience respectively, and 6+ years with embedded systems and strong C/C++ and Python skills. Hands-on lab bring-up and debugging experience with high-speed signals and protocols such as PCIe and Ethernet is expected.
oscilloscope, JTAG debugger, EDA tools, Jira, Confluence
Digital Design Verification Engineer, Staff
Toronto, ONQualcomm Canada ULC
4+ ansCandidates need a bachelor's degree in a science or engineering field with 4+ years of ASIC design or verification experience, or an equivalent master's or PhD with less experience. Strong SystemVerilog, UVM and scripting skills and proven leadership and communication are required.
Verilog, SystemVerilog, UVM, Python, Perl, C/C++