Firmware Engineer – SerDes PHY (all levels)
Toronto, ONQualcomm Canada ULC
6+ ansCandidates need an engineering or computer science degree and 4 to 6+ years of software engineering experience, depending on degree level. They also need at least 3 years of programming experience in languages such as C, C++, Java or Python.
JTAG debuggers, git, Verilog, SystemVerilog
Design Verification Engineer — Memory Subsystem (Vancouver)
Vancouver, BCQualcomm Canada ULC
3+ ansCandidates need a bachelor's or master's degree in an engineering or computer science field and 3 to 10 years of chip or subsystem verification experience. Hands-on skill with Verilog, SystemVerilog, UVM and assertions is required, and knowledge of memory standards such as DDR, LPDDR and HBM is preferred.
Verilog, SystemVerilog, UVM, SystemVerilog Assertions, waveform viewers
Senior ASIC Design Engineer, Compute DSP/AI Processors (multiple levels)
Markham, ONQualcomm Canada ULC
2+ ansCandidates need a bachelor's, master's or PhD in engineering or science with 2 to 4+ years of ASIC design or verification experience, depending on degree. Strong SystemVerilog, synthesis and design tool skills and an understanding of high-performance processor design are needed.
SystemVerilog, VCS, Synopsys Design Compiler, Cadence, Mentor, Linting tools