AI/ML Design Verification Engineer (Staff)
Markham, ONSur place
Qualcomm Canada ULC
4+ ansCandidates need a bachelor's degree plus 4+ years of ASIC work, or a master's with 3+ years, or a PhD with 2+ years. They need SystemVerilog Assertions, a formal verification tool, UVM or SystemVerilog testing, and scripting in Python, Perl, Tcl or shell.
VC Formal, JasperGold, Questa Formal, SystemVerilog, UVM, Python