FY27 Intern - Design Automation & Quality Assurance Engineering Intern - Canada (16 months)
Toronto, ONQualcomm Canada ULC
1+ ansCandidates need to be pursuing a bachelor's degree in electrical, computer or related engineering, with programming skill in at least one language such as Python. Strong problem-solving, attention to detail, teamwork and communication abilities are required.
Python, Cadence Virtuoso, Siemens Calibre, Git, Linux
Telemetry Firmware/Driver Development, Staff
Markham, ONQualcomm Canada ULC
4+ ansCandidates need a bachelor's degree in engineering, computer science or a related field with 4+ years of software engineering experience, or a master's with 3+ years, or a PhD with 2+ years. They also need 2+ years programming in C, C++, Java or Python.
Git, Perforce
Sr Staff/Principal DevOps Engineer, Machine Learning Infrastructure and Performance
Markham, ONQualcomm Canada ULC
6+ ansCandidates need deep Linux, CI/CD, Docker and Python skills, plus 6 to 8+ years of experience depending on degree. Familiarity with GitHub Actions, pytest, FastAPI, PostgreSQL and ONNX is an asset.
GitHub Actions, Docker, Git LFS, pytest, FastAPI, PostgreSQL
Staff ASIC Verification Engineer, Low Power AI
Markham, ONQualcomm Canada ULC
4+ ansQualcomm Canada ULC needs candidates with a relevant degree and 4+ years of ASIC work (3+ with a master's, 2+ with a PhD). Expert knowledge of Verilog, VHDL and SystemVerilog UVM is required, plus solid C skills.
SystemVerilog, UVM, Verilog, VHDL, SystemC, Perl
DFT Engineer, Principal
Toronto, ONQualcomm Canada ULC
8+ ansCandidates need 10+ years of SoC experience in RTL, DFT or front-end roles, and extensive use of Siemens, Synopsys and Cadence DFT tools. Strong Verilog, VHDL and SystemVerilog skills, knowledge of JTAG, iJTAG and BIST standards, and TCL or Python scripting are expected.
Siemens DFT tools, Cadence DFT tools, Verilog, VHDL, SystemVerilog, TCL
Firmware Engineer, Principal
Toronto, ONQualcomm Canada ULC
8+ ansCandidates need an engineering or computer science degree plus 8+ years of software engineering experience, or a master's with 7+ years. They also need 4+ years coding in C, C++, Java or Python, strong embedded firmware and lab debug skills, and team leadership experience.
Git, Python, RISC-V
DFT Engineer (Senior to Staff level)
Toronto, ONQualcomm Canada ULC
10+ ansCandidates need a bachelor's degree in an engineering or computer science field and 10+ years of SoC design experience in RTL, DFT or front-end work. They need strong knowledge of DFT tools, Verilog, VHDL and SystemVerilog, and standards such as JTAG, iJTAG and BIST.
Siemens DFT tools, Cadence DFT tools, Verilog, VHDL, SystemVerilog, TCL
High Speed Validation Engineer, Senior
Toronto, ONQualcomm Canada ULC
2+ ansCandidates need a bachelor's degree with 2+ years of ASIC work, or a master's with 1+ year, or a PhD. They need hands-on high speed interface validation, SerDes knowledge, Python or C/C++ scripting, and lab instrument automation.
BERT, Logic analyzer, VNA, Power supplies, Multimeter, SIGTEST
Firmware Engineer, Staff
Toronto, ONQualcomm Canada ULC
6+ ansCandidates need a bachelor's, master's or PhD in a related field plus 4, 3 or 2 years of software engineering experience respectively, and 6+ years with embedded systems and strong C/C++ and Python skills. Hands-on lab bring-up and debugging experience with high-speed signals and protocols such as PCIe and Ethernet is expected.
oscilloscope, JTAG debugger, EDA tools, Jira, Confluence
Software Engineer, Senior
Toronto, ONQualcomm Canada ULC
2+ ansCandidates need a Bachelor's degree in an engineering or computer field with 2+ years of software experience, or a Master's with 1+ year, or a PhD. They need 2+ years of programming experience in languages such as C, C++, Java or Python, plus knowledge of Linux, CI/CD, testing and basic networking.
JavaScript, React, Python, C++, MongoDB, GitLab
Digital Design Verification Engineer, Staff
Toronto, ONQualcomm Canada ULC
4+ ansCandidates need a bachelor's degree in a science or engineering field with 4+ years of ASIC design or verification experience, or an equivalent master's or PhD with less experience. Strong SystemVerilog, UVM and scripting skills and proven leadership and communication are required.
Verilog, SystemVerilog, UVM, Python, Perl, C/C++