Mixed Signal Design Engineer
Ottawa, ONCiena Canada ULC
Ciena Canada ULC needs a degree in electrical or computer engineering, computer science or a related science. Candidates need CMOS or BiCMOS design experience and skill with Cadence, Synopsys and Siemens EDA tools, plus SystemVerilog, Verilog-AMS, Python and C/C++.
Cadence Virtuoso, Cadence Xcelium, Cadence AMS, Synopsys VCS, Synopsys StarRC, Siemens Questa
R&D Optical Product Ramp Engineer
Ottawa, ONCiena Canada ULC
2+ ansCandidates need a bachelor's degree in electrical, computer or engineering physics, and 2 to 5 years of hardware or electronic-product experience. Statistical analysis skills, scripting in Python or MATLAB, hands-on lab ability and strong communication are required.
Python, MATLAB, Optical test equipment, Electrical test equipment, Automated test platforms
ASIC Front End Implementation Engineer
Ottawa, ONCiena Canada ULC
5+ ansCandidates need a B.Sc. in electrical or computer engineering and 5+ years of ASIC digital design and DFT experience. They must have hands-on DFT and synthesis tool skills and be able to work well in engineering teams.
Synthesis tools, Static timing analysis tools, DFT tools, EDA tools