Verification Engineer
Markham, ONTemps plein
AM
Advanced Micro Devices, Inc
Candidates need strong SystemVerilog and UVM skills, solid ASIC/SoC verification experience, and familiarity with constrained-random, coverage-driven and formal (SVA) methods. A bachelor's or master's in computer or electrical engineering is required.
Synopsys VCS, Cadence IES, Cadence IEV, Jasper, VC-Formal, Magellan