SoC DFX Scan / ATPG Engineer
Markham, ONAMD, Inc.
Candidates need a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field, plus strong DFT fundamentals and ASIC design flow knowledge. Scripting in Python, Perl, Tcl, or Shell and Verilog/SystemVerilog familiarity are preferred.
Verilog, SystemVerilog, Python, Perl, Tcl
SoC Physical Design Implementation Lead
Markham, ONAMD, Inc.
Candidates need deep hands-on experience with place and route, static timing analysis, clock distribution and physical verification on large SoCs. Advanced process nodes, 3D stacking, and Synopsys, Cadence or Siemens CAD tools are preferred, along with Tcl, Perl or Shell scripting.
Synopsys tools, Cadence tools, Tcl, Perl, Shell
3D IC and ADVANCED PACKAGING CAD ENGINEER
Markham, ONAMD, Inc.
Candidates need a computer or electrical engineering degree, experience in 3D-IC and advanced packaging, and hands-on work with Synopsys or Cadence EDA tools. Strong Python, TCL and Perl scripting on Linux, plus experience applying AI or LLMs to CAD or hardware design, are preferred.
Synopsys 3DIC Compiler, Synopsys EDA tools, Cadence EDA tools, Verilog, UPF, Python
SoC Data Path Engineer
Markham, ONAMD, Inc.
Candidates need a bachelor's or master's degree in electrical or computer engineering and experience in post-silicon validation or hardware debug. Strong knowledge of SoC architecture, coherency and memory, plus programming in C/C++ or Python, is also needed.
JTAG tools, Scan dump analysis tools
DFT Design Engineer
Markham, ONAMD, Inc.
Candidates need a Bachelor's or Master's in computer or electrical engineering, strong scripting skills in Perl, Python, TCL or C++, knowledge of digital circuits and VLSI, and good communication skills.
Perl, Python, TCL, C++, SQL
SoC DFX Scan / ATPG Engineer
Ottawa, ONAMD, Inc.
Candidates need a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field, plus strong DFT fundamentals and ASIC design flow knowledge. Scripting in Python, Perl, Tcl, or Shell and Verilog/SystemVerilog familiarity are preferred.
Verilog, SystemVerilog, Python, Perl, Tcl
Design Verification Engineer
Markham, ONAMD, Inc.
AMD asks for advanced ASIC functional verification experience and hands-on work on multiple projects or tapeouts. Candidates need Verilog, SystemVerilog, UVM, scripting skills, and a Bachelor's or Master's in Computer or Electrical Engineering.
Verilog, UVM, Makefiles, Perl, Python, Ruby
RTL/Firmware Design Engineer
Markham, ONAMD, Inc.
Candidates need a Bachelor's or Master's in computer engineering, electrical engineering, computer science or a related field. Embedded C/C++, reading Verilog or SystemVerilog, Python scripting and analytical problem-solving are preferred.
Verilog, SystemVerilog, Git, Perforce, Jenkins, Python
Silicon Design Engineer
Markham, ONAMD, Inc.
Candidates need a bachelor's degree in electrical or computer engineering, with a master's or PhD preferred. AMD wants hands-on ASIC firmware and hardware verification experience with UVM, SystemVerilog, C/C++ and bus protocols such as AXI and AHB.
UVM, Verilog, C-DPI, Python, Perl, Make
Principal Systems Validation Engineer – Data Center GPU System Stress
Markham, ONAMD, Inc.
AMD needs an engineer with a Bachelor's or Master's in Computer or Electrical Engineering, extensive SoC, board and server platform knowledge, and proven validation strategy and debug experience. Scripting skills in Python, C/C++ or Perl and working knowledge of Linux and Windows servers are required.
Linux, Windows Server, Python, C++, Perl, Ruby
Lead Physical Design Engineer, Place & Route
Markham, ONAMD, Inc.
Candidates need deep place-and-route and physical design experience on complex, advanced-node chips, plus scripting skills in TCL, Perl or Shell. A bachelor's or master's degree in electrical, computer or a related engineering field is preferred.
Synopsys Fusion Compiler, Cadence, Siemens EDA, TCL, Perl, Shell
SoC Lead Engineer – LEC & Low Power Signoff
Markham, ONAMD, Inc.
Candidates need proven SoC implementation and tapeout experience, in-depth LEC and low power static verification skills, and hands-on use of Formality or Conformal, VC-LP or CLP, and Design Compiler or Fusion Compiler. Verilog, VHDL, UPF, Tcl, Perl and Python skills and a BS/MS in electrical engineering or a related field are also expected.
Synopsys Formality, Cadence Conformal, Synopsys VC-LP, Cadence Conformal Low Power, Design Compiler, Fusion Compiler
Senior ASIC RTL Design Engineer, AI Networking IP
Ottawa, ONAMD, Inc.
Candidates need proven RTL design experience in Verilog or SystemVerilog, ASIC or FPGA delivery experience, and a bachelor's or master's degree in computer or electrical engineering. Networking or high-speed interface knowledge, such as Ethernet or PCIe, is preferred.
Verilog, SystemVerilog, Synopsys tools, Cadence tools, Siemens (Mentor) tools, Python
Principal ASIC Design Engineer
Markham, ONAMD, Inc.
Candidates need a track record of leading ASIC or silicon designs through multiple product tape-outs, plus deep RTL and microarchitecture experience. Strong communication skills and the ability to lead technical reviews are also required.
Verilog, SystemVerilog, Python, Perl, Tcl
Design Verification Lead
Markham, ONAMD, Inc.
Candidates need a bachelor's or master's degree in electrical or computer engineering, computer science or a related field, plus UVM and SystemVerilog experience and knowledge of high-speed protocols such as PCIe, CXL or Ethernet. Scripting in Python or Perl and technical leadership skills are also needed.
SystemVerilog, Verilog, UVM, Python, Perl