PST Validation Engineer
Markham, ONQualcomm Technologies, Inc.
2+ ansCandidates need a bachelor's degree in science or engineering and 2+ years of ASIC design, verification or validation work, or a master's with 1+ year. They need knowledge of mobile chip architecture, regression and PVT testing, and C and Python programming.
Lauterbach Trace32, JTAG, Python, C
Emulation Performance/Debug Engineer
Markham, ONQualcomm Technologies, Inc.
2+ ansCandidates need a bachelor's degree in science or engineering with 2+ years of ASIC work, or a master's with 1+ year. Experience with emulation platforms, Verilog/SystemVerilog, C, Python, TCL and FPGA timing closure is preferred.
Veloce, Palladium, Xilinx FPGA, Intel FPGA, JTAG, Python
Pre-Silicon Validation Engineer
Markham, ONQualcomm Technologies, Inc.
Candidates need a Bachelor's or Master's degree in an engineering, computer science or related field, 0-2+ years in ASIC verification, FPGA prototyping or hardware emulation, and strong skills in SystemVerilog, C/C++, Linux, and Python. Experience with RTL debugging and SoC architectures is also required.
SystemVerilog, C/C++, Python, Linux, Cadence Palladium, Siemens Veloce
Senior Emulation Performance Methodology & Debug Engineer
Markham, ONQualcomm Technologies, Inc.
4+ ansCandidates need a bachelor's, master's or PhD in a science or engineering field with 4+, 3+ or 2+ years of ASIC design or verification experience respectively. Preferred: 5+ years in emulation and silicon environments, plus Verilog/SystemVerilog, C, Python, TCL and FPGA timing closure skills.
Veloce, Palladium, FPGA prototyping, JTAG debugger, Xilinx FPGA, Intel FPGA
SoC Clock & Power Management Validation Lead, Staff (AI Accelerator Platform)
Markham, ONQualcomm Technologies, Inc.
5+ ansQualcomm Technologies needs candidates with a bachelor's degree in engineering and 5+ years in SoC validation or related areas. They must know clock or power validation, C and Python, lab instruments such as oscilloscopes, and JTAG debug on ARM-based SoCs.
Oscilloscope, Logic analyzer, Multimeter, Python, C, Perl
SoC Debug Engineer, Senior Staff
Markham, ONQualcomm Technologies, Inc.
9+ ansCandidates need 9+ years of pre-silicon and post-silicon bring-up and debug experience, RTL understanding, and hands-on use of JTAG and lab equipment such as logic analyzers and oscilloscopes. A Master's in Computer or Electrical Engineering is required, along with the stated years of ASIC design or validation experience.
JTAG, Logic analyzer, Signal generator
SoC Debug Engineer, Staff
Markham, ONQualcomm Technologies, Inc.
6+ ansCandidates need 6+ years of pre-silicon and post-silicon bring-up and failure analysis experience, plus RTL understanding and JTAG and lab equipment skills. A Master's in Computer or Electrical Engineering is required, along with ASIC experience.
JTAG, Logic analyzer, Signal generator
SoC Infrastructure/NoC, Power & Performance Validation Engineer
Markham, ONQualcomm Technologies, Inc.
5+ ansCandidates need several years of ASIC design, validation or verification experience, with a strong grasp of on-chip interconnects, performance and power. Strong programming in C, C++, Python and assembly, plus JTAG and kernel debugging, are expected.
JTAG debuggers, kernel debuggers, state dump scripts, Python, C, C++