2+ ansCandidates need a bachelor's degree in science or engineering and 2+ years of ASIC design, verification or validation experience, or an equivalent graduate degree. Strong Python or C scripting, lab debug skills with oscilloscopes and logic analyzers, and familiarity with JTAG and kernel debuggers are needed.
5+ ansCandidates need hands-on experience building and optimizing language models in PyTorch and ONNX, a deep understanding of transformer architectures, and strong Python skills. A Master's degree in a related field and 5+ years of hardware, software or systems experience are required.
3+ ansCandidates need a degree in engineering or computer science and several years of ASIC or silicon validation work. They need strong debugging skills, solid C/C++ and Python, and a good grasp of SoC architecture and memory systems.
4+ ansCandidates need hands-on experience with LLM serving packages, strong PyTorch and Python skills, and solid computer science fundamentals. A bachelor's degree with 4+ years of experience, a master's with 3+ years, or a PhD with 2+ years is required.
2+ ansCandidates need a bachelor's degree in science or engineering and 2+ years of ASIC design, verification or validation work, or a master's with 1+ year. They need knowledge of mobile chip architecture, regression and PVT testing, and C and Python programming.
5+ ansCandidates need at least 5 years in DDR or memory subsystem validation or silicon bring-up, plus knowledge of LPDDR architectures, memory controllers and PHYs, and strong post-silicon debug skills. Qualcomm also requires a bachelor's, master's or PhD and C/C++ proficiency.
2+ ansCandidates need a bachelor's degree in science or engineering with 2+ years of ASIC work, or a master's with 1+ year. Experience with emulation platforms, Verilog/SystemVerilog, C, Python, TCL and FPGA timing closure is preferred.
Candidates need a Bachelor's or Master's degree in an engineering, computer science or related field, 0-2+ years in ASIC verification, FPGA prototyping or hardware emulation, and strong skills in SystemVerilog, C/C++, Linux, and Python. Experience with RTL debugging and SoC architectures is also required.
7+ ansQualcomm needs a candidate with 7+ years of silicon validation or platform bring-up experience and deep knowledge of NoCs, AXI, memory hierarchy, power modes and debug. A degree in engineering or computer science is required, with embedded C/C++, Python and assembly skills.
5+ ansQualcomm Technologies needs candidates with a bachelor's degree in engineering and 5+ years in SoC validation or related areas. They must know clock or power validation, C and Python, lab instruments such as oscilloscopes, and JTAG debug on ARM-based SoCs.
7+ ansCandidates need a bachelor's degree in science or engineering with 7+ years of related experience, or the equivalent advanced degree with fewer years. Strong C++, Linux, CAD software development and VLSI or ASIC design skills are preferred.
8+ ansCandidates need 8+ years of SoC validation, bring-up, or system software experience, deep knowledge of modern SoC architectures such as ARM CPUs, memory and interconnects, and proven pre- and post-silicon validation and debug skills. Leadership of geographically distributed teams is required.
8+ ansCandidates need 8+ years of silicon validation or platform bring-up experience, strong C and Assembly skills, and bare-metal embedded knowledge. A BS, MS or PhD in an engineering or computer science field is required, plus the minimum years of ASIC work listed for each degree.
FPGA, Verilog, VHDL, Python, Linux shell, development boards
9+ ansCandidates need 9+ years of pre-silicon and post-silicon bring-up and debug experience, RTL understanding, and hands-on use of JTAG and lab equipment such as logic analyzers and oscilloscopes. A Master's in Computer or Electrical Engineering is required, along with the stated years of ASIC design or validation experience.
6+ ansCandidates need 6+ years of pre-silicon and post-silicon bring-up and failure analysis experience, plus RTL understanding and JTAG and lab equipment skills. A Master's in Computer or Electrical Engineering is required, along with ASIC experience.
5+ ansCandidates need several years of ASIC design, validation or verification experience, with a strong grasp of on-chip interconnects, performance and power. Strong programming in C, C++, Python and assembly, plus JTAG and kernel debugging, are expected.
JTAG debuggers, kernel debuggers, state dump scripts, Python, C, C++