Principal SerDes System/DSP Design Engineer
Ottawa, ON +1Ciena Canada ULC
8+ ansCandidates need a Ph.D. in Electrical Engineering with 8+ years in high-speed serial link or communication system design. Required skills include SerDes DSP design, adaptive equalization, MLSD, timing recovery, FEC modeling, IMDD optical familiarity, and MATLAB, Python or C/C++.
MATLAB, Python, C/C++
Senior Analog RF Design Engineer
Ottawa, ONCiena Canada ULC
5+ ansCiena needs a Master's degree in electrical engineering or equivalent and 5 to 10 years of RF analog circuit design for telecom. Candidates need high-speed RF, op-amp and BiCMOS design experience, plus Cadence and mixed-signal simulation skills.
Cadence Virtuoso, Cadence AMS, Calibre, HFSS, EMX, VNA
Principal Analog Circuit Designer
Ottawa, ONCiena Canada ULC
7+ ansCandidates need a Master's degree in an engineering or applicable science field and 7+ years of advanced CMOS or BiCMOS design experience. They must have mm-wave analog design experience and skill with Cadence Virtuoso, Calibre, STAR-RC and MMSIM.
Cadence Virtuoso, Calibre, STAR-RC, MMSIM, HFSS, EMX
Senior Analog Layout Engineer
Ottawa, ONCiena Canada ULC
1+ ansCandidates need a bachelor's degree in electrical engineering or a related field and 1 to 5 years of analog or mixed-signal layout experience. They must know deep sub-micron CMOS and FinFET design, and use industry layout tools such as Cadence Virtuoso and Siemens Calibre.
Cadence Virtuoso, Siemens Calibre, Ansys Totem
Senior ASIC Design Engineer - Client IP
Ottawa, ONCiena Canada ULC
5+ ansCandidates need an engineering degree at the bachelor or master level and 5+ years of SystemVerilog design and digital synthesis, timing closure and clock-crossing experience. Strong independent problem solving, English communication, and knowledge of verification and timing/power/area trade-offs are required.
Git, Jira, Python, Make, bash
Embedded Software Engineer - New Grad
Ottawa, ONCiena Canada ULC
Candidates need to be enrolled in a bachelor's or master's program in computer or electrical engineering or computer science, with prior internship, co-op or applied project experience. They must code in C or C++, use Python or bash, and know git and software design patterns.
git, Jira, Gerrit, Bitbucket, gdb, Google Test
Senior ASIC Verification Engineer, onsite Kanata
Ottawa, ONCiena Canada ULC
Ciena Canada ULC needs candidates with an engineering or science degree at the BEng/BSc or MEng/MSc level and familiarity with formal verification. Candidates should know standards such as OTN, B100G and Ethernet, and programming in Python, C, C++ or SystemC.
Python, C, C++, Make, bash