Emplois “Cadence EDA tools” au Canada – Page 2

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• 28j

  IC design Implementation and SignOff Architect, (STA SignOff)

  Canada

  Temps plein

  C

  Cadence

  15+ ansCandidates need 15+ years of IC design implementation and signoff experience, deep advanced-node STA and ECO skills, and strong scripting in Tcl, Python or Perl. A BS or MS in electrical or computer engineering is required.

  Tempus, Certus, QRC

  1 mois

  Firmware Design Engineer

  Mount Royal, SK

  74k $/anTemps plein

  C

  Cadence

  Solide programmation en C/C++ et Python; Compréhension des principes de communication filaire; Connaissance des circuits mixtes et du traitement numérique du signal

  Firmware, Work independently, Leadership, C, C++, Python

  1 mois

  Analog CAD Engineering specialist

  Mount Royal, SK +5

  Temps plein

  C

  Cadence

  Candidates need a BSEE or MSEE, prior experience in analog CAD support, and a strong understanding of circuit and layout design. Excellent communication, presentation and customer service skills are also required.

  Cadence Virtuoso, Cadence Pegasus, Cadence Quantus, Cadence Composer Schematic, Virtuoso Layout

  1 mois

  Ingénieur en conception de micrologiciel - Firmware Design Engineer

  Mount Royal, SK

  74k $/anTemps plein

  C

  Cadence

  Programmation solide en C/C++ et Python; Connaissance des communications filaires; Connaissance de la conception de circuits mixtes et du traitement numérique du signal

  Firmware, Work independently, Leadership, C, C++, Python

  1 mois

  Ingénieur en conception de micrologiciel - Firmware Design Engineer

  Mount Royal, SK

  74k $/anTemps plein

  C

  Cadence

  Programmation solide en C/C++ et Python; Connaissance des communications filaires; Connaissance de la conception de circuits mixtes et du traitement numérique du signal

  Firmware, Work independently, Leadership, C, C++, Python

• 1 mois

  Physical Design Engineer - Synth, Senior

  Télétravail au Canada

  TélétravailTemps plein

  

  Positron AI

  8+ ansCandidates need 8+ years of ASIC implementation experience, including at least two tapeouts, and strong synthesis and timing-closure experience on large designs. Expertise with Genus or Design Compiler, SDC constraints, Tcl and Python scripting, and advanced process nodes (7nm and below preferred) is required.

  Cadence Genus, Synopsys Design Compiler, Tcl, Python

• 1 mois

  FY27 Intern - Design Automation & Quality Assurance Engineering Intern - Canada (16 months)

  Toronto, ON

  Sur placeStage

  

  Qualcomm Canada ULC

  1+ ansCandidates need to be pursuing a bachelor's degree in electrical, computer or related engineering, with programming skill in at least one language such as Python. Strong problem-solving, attention to detail, teamwork and communication abilities are required.

  Python, Cadence Virtuoso, Siemens Calibre, Git, Linux

  1 mois

  DFT Engineer, Principal

  Toronto, ON

  Sur place

  

  Qualcomm Canada ULC

  8+ ansCandidates need 10+ years of SoC experience in RTL, DFT or front-end roles, and extensive use of Siemens, Synopsys and Cadence DFT tools. Strong Verilog, VHDL and SystemVerilog skills, knowledge of JTAG, iJTAG and BIST standards, and TCL or Python scripting are expected.

  Siemens DFT tools, Cadence DFT tools, Verilog, VHDL, SystemVerilog, TCL

  1 mois

  DFT Engineer (Senior to Staff level)

  Toronto, ON

  Sur place

  

  Qualcomm Canada ULC

  10+ ansCandidates need a bachelor's degree in an engineering or computer science field and 10+ years of SoC design experience in RTL, DFT or front-end work. They need strong knowledge of DFT tools, Verilog, VHDL and SystemVerilog, and standards such as JTAG, iJTAG and BIST.

  Siemens DFT tools, Cadence DFT tools, Verilog, VHDL, SystemVerilog, TCL

• 1 mois

  Sr. Manager, Physical Design Engineering, Annapurna Labs

  Toronto, ON

  Temps plein

  AD

  Amazon Development Centre Canada ULC

  10+ ans5+ gestionAmazon Development Centre Canada needs 5+ years leading physical design teams of 8+ engineers and 10+ years of hands-on ASIC/SoC physical design across advanced nodes. Candidates must master both Synopsys and Cadence EDA tools, advanced STA and power integrity, and hierarchical flows for very large SoCs.

  Synopsys Fusion Compiler, ICC2, PrimeTime, StarRC, RedHawk-SC, Cadence Innovus

• 1 mois

  3D IC and ADVANCED PACKAGING CAD ENGINEER

  Markham, ON

  Temps plein

  AM

  Advanced Micro Devices, Inc

  Candidates need a bachelor's or master's degree in computer or electrical engineering, experience with 3D-IC design and advanced packaging, and hands-on work with Synopsys 3DIC Compiler. Strong scripting skills and experience applying AI to CAD or hardware design are also needed.

  Synopsys 3DIC Compiler, Synopsys EDA tools, Cadence EDA tools, Linux/Unix, Python, TCL

  1 mois

  Printed Circuit Board PCB Design and Layout Engineer

  Markham, ON

  Temps plein

  AM

  Advanced Micro Devices, Inc

  Candidates need extensive experience designing complex printed circuit boards with industry PCB design tools such as Cadence Allegro, Altium or Zuken. A bachelor's or master's degree in electrical or computer engineering or a related field is expected, along with the ability to take technical ownership.

  Cadence Allegro, OrCAD, Altium, Zuken, PADS, ODB++

  1 mois

  SoC Lead Engineer – LEC & Low Power Signoff

  Markham, ON

  Temps plein

  AM

  Advanced Micro Devices, Inc

  Advanced Micro Devices needs candidates with proven SoC implementation and tapeout experience, deep knowledge of equivalence checking and low power verification, and hands-on use of industry EDA tools. Strong scripting, debugging, leadership and communication skills are also required, along with a BS or MS in Electrical Engineering, ECE, EEE or a related field.

  Synopsys Formality, Cadence Conformal, Synopsys VC-LP, Cadence Conformal Low Power, Design Compiler, Fusion Compiler

  1 mois

  Lead Physical Design Engineer, Place & Route

  Markham, ON

  Temps plein

  AM

  Advanced Micro Devices, Inc

  Candidates need deep hands-on place-and-route experience on complex chip designs, including timing closure and physical verification. Experience with Synopsys Fusion Compiler, Cadence and Siemens EDA tools, plus TCL, Perl or Shell scripting, is preferred, and a Bachelor's or Master's degree in electrical or computer engineering is preferred.

  Synopsys Fusion Compiler, Cadence, Siemens EDA, TCL, Perl, Shell

• 1 mois

  ASIC Verification Engineer (7745)

  Ottawa, ON

  T

  TSMC

  5+ ansCandidates need a master's or PhD in electrical or computer engineering and 5-10 years of digital verification experience. They should be strong in SystemVerilog, UVM, assertions, Unix/Linux and EDA tools such as VCS or Incisive.

  Synopsys VCS, Cadence Incisive, UVM, Unix/Linux

• 1 mois

  HW & SW Applications Admin 1

  Toronto, ON

  

  Celestica International LP

  5+ ansCandidates need a bachelor's degree in computer science, software or electrical engineering, or a related field, and 5+ years of enterprise IT or application engineering experience, including 2+ years supporting an R&D engineering team. Hands-on experience with EDA/CAD suites, DevOps tools, license management and Linux and Windows environments is required.

  Azure DevOps, Jira, Git, Docker, Kubernetes, PTC Creo

• 1 mois

  Analog and RF Layout Engineer

  Toronto, ON

  

  Capgemini

  6+ ansCandidates need 6+ years of analog and RF IC layout experience for high-speed applications, including advanced FinFET nodes (7nm and below). Hands-on use of Cadence, Mentor and Synopsys EDA tools and knowledge of floorplanning, routing and electromigration are required.

  Cadence, Mentor, Synopsys

  1 mois

  Analog and RF Layout Engineer

  Toronto, ON

  

  Capgemini

  6+ ansCandidates need 6+ years of analog, RF or mixed-signal IC layout experience, including advanced FinFET nodes at 7nm and below. They need hands-on skill with Cadence, Synopsys or Siemens EDA tools and strong knowledge of DRC, LVS and reliability constraints.

  Synopsys, Siemens EDA, Mentor Graphics

• 1 mois

  Senior Physical Design Engineer - P&R

  Ottawa, ON

  TélétravailTemps plein

  

  BTA Design Services: specializes in ASIC and FPGA design and verification services, custom IP development, embedded software, and DevOps capabilities creation.

  8+ ansCandidates need 8 or more years of ASIC digital place-and-route experience, recent hands-on work with Synopsys and Cadence tools, and knowledge of advanced FinFET nodes. Scripting skills and strong written communication for remote teamwork are also required.

  Synopsys, Cadence, PrimeTime, StarRC, RedHawk, Calibre

• 1 mois

  SMTS Logic Design

  Montréal, QC

  

  Rambus: As an industry pioneer with over 30 years experience, Rambus is a premier provider of chips & silicon IP.

  8+ ansCandidates need a BS, MS or PhD in electrical or computer engineering, 8+ years of ASIC/SoC logic design experience, and expert SystemVerilog skills. Experience with synthesis, timing closure and PCIe Gen5/Gen6/Gen7 is preferred.

  SystemVerilog, Synopsys Design Compiler, Synopsys Fusion Compiler, Cadence Genus, SpyGlass, Questa

• 1 mois

  Junior CAD PCB Technician

  Sainte-Anne-de-Bellevue, QC

  Temps plein

  

  MDA

  Candidates need an AEC or DEC in electrical engineering or equivalent, plus a good understanding of PCB fabrication and assembly. Experience with EDA layout tools such as Xpedition, Allegro, Altium or OrCAD, multilayer board design and French-English fluency are assets.

  Mentor Graphics Xpedition, Cadence Allegro, PADS Layout, Altium, OrCAD

• 1 mois

  Principal Packaging Engineer

  Ottawa, ON +2

  Temps plein

  S

  Semtech_Canada_Corporation

  8+ ansSemtech Canada needs a bachelor's degree in electrical or physics engineering and 8+ years as a package or signal integrity engineer. Candidates need deep high-speed design knowledge and hands-on experience with EDA tools and VNA and TDR measurement equipment.

  Keysight ADS, Cadence APD, Cadence SiP, Ansys HFSS, Vector Network Analyzer, Time-Domain Reflectometer

• 1 mois

  Staff Physical Design Engineer

  Télétravail au Canada

  Télétravail

  

  EnCharge AI

  10+ ansCandidates need a Bachelor's or Master's in electrical, computer or a related engineering field and 10 to 15 years of physical design experience. Strong Cadence, static timing analysis, low-power and EM/IR skills, plus Tcl or Python scripting, are required.

  Cadence design tools, Tcl, Python

• 1 mois

  Software Development Team Lead

  Montréal, QC

  HybrideTemps plein

  

  Maya HTT

  4+ ansCandidates need a degree in computer science, mechanical engineering or a related field, plus 4+ years as a software developer. Strong C#.NET, Python or C++ skills, object-oriented practice, and excellent English communication are required.

  Git, JIRA, NX Open, Teamcenter, Cadence, Xpedition

14 entreprises