RTL Design Engineer
Markham, ONAMD, Inc.
Candidates need a strong background in RTL design, Verilog and SystemVerilog, and scripting in Python, Tcl, Perl, Ruby, or Make. Experience with AXI, AHB, AMBA protocols, ASIC design tools, and a Bachelor's or Master's degree in electrical or computer engineering are expected.
Verilog, SystemVerilog, C-DPI, FPGA, ASIC simulation and synthesis tools
ASIC Design Engineer, PCIe IP Enablement
Markham, ONAMD, Inc.
Candidates need hands-on ASIC hardware design experience with end-to-end ownership of complex digital IP through tape-out. Strong RTL and Verilog skills, synthesis and CDC tool experience, and knowledge of low-power design are expected.
Verilog, UPF, CPF
Silicon Design Engineer
Markham, ONAMD, Inc.
Candidates need a bachelor's degree in electrical or computer engineering, with a master's or PhD preferred. AMD wants hands-on ASIC firmware and hardware verification experience with UVM, SystemVerilog, C/C++ and bus protocols such as AXI and AHB.
UVM, Verilog, C-DPI, Python, Perl, Make
Silicon Design Engineer - Technical Lead
Markham, ONAMD, Inc.
AMD needs candidates with experience in I/O protocols such as USB, PCIe and CXL, plus micro-architecture and RTL design for multi-clock, high-frequency, low-power designs. A master's or bachelor's in electrical engineering or equivalent is preferred.
Python, Perl
RTL Design Engineer
Markham, ONAMD, Inc.
Candidates need experience with I/O protocols such as USB, PCIe and CXL, plus RTL design for multi-clock, high-frequency, low-power designs. A bachelor's or master's degree in electrical engineering or equivalent is preferred.
Python, Perl
Senior ASIC RTL Design Engineer, AI Networking IP
Ottawa, ONAMD, Inc.
Candidates need proven RTL design experience in Verilog or SystemVerilog, ASIC or FPGA delivery experience, and a bachelor's or master's degree in computer or electrical engineering. Networking or high-speed interface knowledge, such as Ethernet or PCIe, is preferred.
Verilog, SystemVerilog, Synopsys tools, Cadence tools, Siemens (Mentor) tools, Python
Principal ASIC Design Engineer
Markham, ONAMD, Inc.
Candidates need a track record of leading ASIC or silicon designs through multiple product tape-outs, plus deep RTL and microarchitecture experience. Strong communication skills and the ability to lead technical reviews are also required.
Verilog, SystemVerilog, Python, Perl, Tcl