Digital - Staff Digital Design Engineer - PHY
CanadaSur placeTemps plein
E
Eliyan
8+ ansEliyan needs 8+ years of digital frontend design with 4+ years in PHY or high-speed interfaces, and 3+ tapeouts as design lead at 7nm or below. Candidates need expert SystemVerilog, synthesis, CDC and UCIe or DDR/SerDes knowledge.
SystemVerilog, Synopsys Design Compiler, Synopsys Fusion Compiler, Cadence Genus, UPF, SDC
Digital - Digital Design Engineer (title will reflect experience)
CanadaSur placeTemps plein
E
Eliyan
5+ ansCandidates need a degree in electrical engineering or a related field and 5+ years of high-speed digital design experience. They need strong SystemVerilog and synthesis skills, knowledge of IEEE 802.3 Ethernet standards, and startup experience.
SystemVerilog, SDC constraints