RTL Design Engineer - AI Tools
Toronto, ON100–175 $/h
Mercor
3+ ansCandidates need 3 to 10 years of digital RTL design or design verification experience, strong Verilog, SystemVerilog and UVM skills, and solid digital design fundamentals. Experience with ASIC design flows and EDA tools is also required.
Verilog, SystemVerilog, UVM, EDA tools