FPGA Design Engineer
Nepean, ONActalent: Actalent is an operating company of Allegis Group, the global leader in talent solutions.
5+ ansCandidates need 5+ years of ASIC or FPGA design experience, strong SystemVerilog skills, and hands-on Cadence simulation and design debug experience. Experience with synthesis, timing analysis and simulation frameworks is also required.
Xilinx Vivado, Cadence simulation tools, SystemVerilog, VHDL
Senior Test Engineer
Nepean, ONActalent: Actalent is an operating company of Allegis Group, the global leader in talent solutions.
5+ ansActalent needs at least 5 years of automated production test experience, with optical or RF background (fiber optics preferred), NPI or manufacturing experience, and a technical degree. Candidates must know LabVIEW and Python, and should understand fiber optic test instruments such as power meters, spectrum analyzers and OTDRs.
LabVIEW, Python, TestStand, LabWindows CVI, SQL, Power meter
FPGA Design Engineer
Ottawa, ONActalent: Actalent is an operating company of Allegis Group, the global leader in talent solutions.
5+ ansCandidates need 5+ years of ASIC/FPGA design experience, strong SystemVerilog skills, hands-on Cadence simulation experience, and practical debug and timing analysis skills. VHDL, Xilinx Vivado, Python, C/C++, DSP and high-speed interface experience are assets.
SystemVerilog, Xilinx, Vivado, Cadence simulation tools, Python, C