Digital - Digital Design Engineer (title will reflect experience)
CanadaSur placeTemps plein
E
Eliyan
5+ ansCandidates need a degree in electrical engineering or a related field and 5+ years of high-speed digital design experience. They need strong SystemVerilog and synthesis skills, knowledge of IEEE 802.3 Ethernet standards, and startup experience.
SystemVerilog, SDC constraints
Digital - ASIC Design Automation & Integration Engineer
CanadaSur placeTemps plein
E
Eliyan
5+ ansEliyan needs candidates with a relevant engineering degree and five or more years in ASIC or SoC design or design automation. Candidates must know lint, CDC and synthesis tools, SystemVerilog, Python, Tcl, Git, Linux and CI/CD pipelines, and be authorized to work in the United States or Canada.
SpyGlass, QuestaLint, Genus, Fusion Compiler, Jenkins, Git