DSP Application Engineer, Principal
Ottawa, ONQualcomm Canada ULC
12+ ansCandidates need an electrical engineering degree and years of hardware applications or semiconductor experience, with deep knowledge of PAM4 signaling, DSP equalization, SerDes, Ethernet and optical communications. Hands-on skill with oscilloscopes, BERTs and VNAs, plus Python or C automation, is required.
Oscilloscope, BERT, VNA, Python, C
Verification Engineer (Engineer–Senior Level)
Toronto, ONQualcomm Canada ULC
2+ ansCandidates need a bachelor's degree in science or engineering with 2+ years of ASIC design or verification experience, or a master's with 1+ year, or a PhD. Strong SystemVerilog and UVM skills, constrained random verification experience and clear communication are required.
SystemVerilog, UVM, Python, Perl, C/C++, GNU Make
Staff Engineer, Physical Design/Implementation
Toronto, ONQualcomm Canada ULC
3+ ansCandidates need a Master's degree with 3+ years or a Bachelor's with 4+ years of ASIC physical design experience. They need hands-on skill with industry chip design tools and strong knowledge of timing, power and clocking.
Cadence Innovus, Synopsys ICC2
Engineer
Markham, ONQualcomm Canada ULC
1+ ansCandidates need a bachelor's degree in engineering or a related field, plus 6 months to 2 years of experience in chip design, VLSI or digital design, including internships. They should understand digital logic and timing, know basic physical design steps, and have scripting skills in Python, Tcl, Perl or Shell.
Verilog, SystemVerilog, EDA tools
Sr ASIC Design Verification Engineer, Low Power AI
Markham, ONQualcomm Canada ULC
2+ ansQualcomm Canada ULC needs candidates with a bachelor's, master's or PhD and 2 to 4+ years of ASIC work, depending on degree. Expert skill in Verilog, SystemVerilog, UVM and C, plus a deep understanding of ASIC/VLSI concepts, is required.
SystemVerilog, UVM, Verilog, VHDL, SystemC, Perl
SOC Design Engineer
Markham, ON +2Qualcomm Canada ULC
4+ ansCandidates need a degree in science or engineering and 4+ years of ASIC design, verification or integration work, with strong digital front-end design skills in Verilog, SystemVerilog and VHDL. Experience with power domains, clock domain crossing, low-power design and chip design tools is needed.
Spyglass, Design Compiler, Cadence LEC, Perl, TCL