Senior ASIC Design Verification Engineer - LPU
Télétravail au CanadaNVIDIA Canada Dev. Inc.
8+ ansCandidates need a bachelor's degree in electrical engineering, computer science or computer engineering, or equivalent experience, plus 8 or more years in the industry. They need strong skills in SystemVerilog, UVM and chip design tools.
VCS, Verdi, SystemVerilog, UVM, Perl, Python
Senior Formal Verification Engineer - LPU
Télétravail au CanadaNVIDIA Canada Dev. Inc.
12+ ansCandidates need a BS, MS or PhD in computer science, computer engineering or electrical engineering, 12+ years of ASIC verification with 8+ years in formal methods, mastery of SystemVerilog Assertions, experience with a major formal tool such as JasperGold or VC Formal, and scripting skills in Tcl or Python.
VC Formal, SystemVerilog, Tcl, Python
Senior ASIC Verification Engineer, Coherent High Speed Interconnect
Toronto, ONNVIDIA Canada Dev. Inc.
3+ ansCandidates need a Bachelor's or Master's degree or equivalent experience, plus 3+ years of verification work. Strong SystemVerilog and UVM skills, C++ and scripting, and coherent interconnect experience are expected.
UVM, C++, VCS, Debussy, GDB