Principal Engineer -Design
Saskatoon, SKTemps plein
MS
MCHP Semiconductor Canada ULC
10+ ansCandidates need 10 years of experience in synthesis, static timing analysis and formal verification, plus tapeout experience on 16nm or smaller processes. Strong scripting skills and a degree in computer science or electrical/VLSI engineering are required.
Cadence Genus, TCL, Perl, Python, UPF, CPF
Senior Engineer II - Physical Design
Burnaby, BC86k–186k $/anTemps plein
MS
MCHP Semiconductor Canada ULC
7+ ansCandidates need a 4-year Electrical or Electronics Engineering degree and 7.5+ years of ASIC development experience. They need hands-on skill in synthesis, static timing and place and route for high-performance designs, plus Python, Perl or TCL scripting.
Verilog, VHDL, Python, Perl, TCL