Senior ASIC (Front End) Design Engineer
Toronto, ONEthernovia, Inc.
10+ ansCandidates need a BS or MS in electrical engineering, computer science or a related field and 10+ years of ASIC RTL design or architecture experience. They must have built complex SoCs, know Verilog/SystemVerilog and simulation tools, and work well both independently and in teams.
Verilog, Perl, TCL, C/C++, Make
Senior ASIC Design Verification Engineer
Télétravail au CanadaEthernovia, Inc.
10+ ansCandidates need a BS or MS in electrical engineering, computer science or a related field, and at least 10 years of ASIC verification experience. Required skills include SystemVerilog, UVM, Python, TCL and C/C++, plus strong debugging and communication abilities.
Verilog, UVM, Python, TCL, C/C++, SystemC