Senior Staff ASIC Design Egineer - AI/ML Hardware IP
Toronto, ONT
Talentlab
6+ ansCandidates need six or more years of ASIC design and integration experience (or a Master's plus five years, or a PhD plus four), strong Verilog/SystemVerilog skills, and experience owning complex SoC blocks. A Bachelor's, Master's or PhD in electrical engineering or a related field is required, and the candidate must be legally authorized to work in Canada.
Verilog, SystemVerilog, VCS, Verdi, Questa, Xcelium