Emplois “System on Chip (SoC)” au Canada – Page 3

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• 28j

  SoC Lead Engineer – LEC & Low Power Signoff

  Markham, ON

  Temps plein

  AI

  AMD, Inc.

  Candidates need proven SoC implementation and tapeout experience, in-depth LEC and low power static verification skills, and hands-on use of Formality or Conformal, VC-LP or CLP, and Design Compiler or Fusion Compiler. Verilog, VHDL, UPF, Tcl, Perl and Python skills and a BS/MS in electrical engineering or a related field are also expected.

  Synopsys Formality, Cadence Conformal, Synopsys VC-LP, Cadence Conformal Low Power, Design Compiler, Fusion Compiler

  28j

  Sr. Manager - RTL Design Manager

  Markham, ON

  Temps plein

  AI

  AMD, Inc.

  AMD needs a leader with experience managing IP or RTL design teams and strong Verilog/SystemVerilog skills. Candidates should know RTL microarchitecture, ASIC verification flows and on-chip protocols such as AXI and AHB, and hold a bachelor's degree in an engineering or computer discipline.

  Verilog, SystemVerilog

• 28j

  Firmware Engineer Intern Summer Co-op

  Vancouver, BC

  45–55 $/h

  AL

  Astera Labs Early Career - North America 2027

  Candidates need a computer science or electrical or software engineering background, at least one co-op term in firmware or embedded software, and coursework or experience with an RTOS. They must know C or C++, Python, git and CI, and have debugged firmware using JTAG or trace logs.

  JTAG, git, PyTest, GoogleTest, gcc, make

  28j

  Firmware Engineer Intern Spring Co-Op

  Vancouver, BC

  45–55 $/h

  AL

  Astera Labs Early Career - North America 2027

  Candidates need a computer science or electrical or software engineering background, at least one co-op term of firmware or embedded development, and coursework or experience with an RTOS. They also need C or C++ firmware skills, Python scripting, and experience with git, code reviews and CI.

  JTAG, git, gcc, make, PyTest, GoogleTest

  28j

  Firmware Engineer Intern Fall Co-op

  Vancouver, BC

  45–55 $/h

  AL

  Astera Labs Early Career - North America 2027

  Astera Labs needs candidates in computer science or electrical or software engineering who have completed a co-op term in firmware or embedded software and have used a real-time operating system. They must know C or C++, Python, git, and code reviews, and be able to debug with JTAG or trace logs.

  JTAG, git, PyTest, GoogleTest, gcc, make

  28j

  DFT Engineering Intern

  Toronto, ON

  35–55 $/h

  AL

  Astera Labs Early Career - North America 2027

  Candidates need coursework or hands-on experience in electrical or computer engineering or a related field, and an understanding of digital logic and RTL. Programming in Verilog, SystemVerilog, Python, Tcl, Perl, C or C++ is needed, plus comfort in a Linux environment.

  Verilog, SystemVerilog, Python, Tcl, Perl, Linux

• 29j

  Product Manager, Display Solutions

  Calgary, AB

  

  SMART Technologies

  5+ ansCandidates need a bachelor's degree in business, engineering, computer science or a related field, and at least five years of product management experience, ideally in hardware or embedded systems. Strong technical depth, communication skills and the ability to influence teams without direct authority are essential.

  Azure DevOps, Product analytics tools

• 1 mois

  ASIC Physical Design Engineer - DFT, Senior

  Télétravail au Canada

  TélétravailTemps plein

  

  Positron AI

  8+ ansPositron AI needs 8+ years of ASIC development with several production tapeouts, deep DFT experience, and hands-on Siemens Tessent. Candidates also need Verilog/SystemVerilog RTL skills, synthesis and gate-level verification, and scripting in Python, Tcl or Perl.

  Siemens Tessent, Verilog, SystemVerilog, Python, Tcl, Perl

  1 mois

  ASIC Architect, Principal (AI Inference)

  Télétravail au Canada

  TélétravailTemps plein

  

  Positron AI

  15+ ansCandidates need 15+ years of ASIC architecture experience, deep expertise in AI accelerators and high-performance SoCs, and hands-on work with memory and interconnect performance models. Strong hardware/software co-design and excellent communication skills are required.

  Machine learning, ML, Communication skills, Firmware, Research

  1 mois

  Physical Design Engineer - Synth, Senior

  Télétravail au Canada

  TélétravailTemps plein

  

  Positron AI

  8+ ansCandidates need 8+ years of ASIC implementation experience, including at least two tapeouts, and strong synthesis and timing-closure experience on large designs. Expertise with Genus or Design Compiler, SDC constraints, Tcl and Python scripting, and advanced process nodes (7nm and below preferred) is required.

  Cadence Genus, Synopsys Design Compiler, Tcl, Python

• 1 mois

  Senior SoC Architect (f/m/d)

  Toronto, ON

  TélétravailTemps plein

  

  Black Semiconductor GmbH

  7+ ansCandidates need 7 to 10 years of SoC or product architecture experience, including taking a product from market requirements to a detailed design. Deep high-speed I/O expertise (SerDes, UCIe, PCIe, Ethernet) and experience with on-chip interconnects are essential.

  Python, C++

• 1 mois

  Digital IC Designer

  Waterloo, ON

  Temps plein

  

  onsemi: With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety,…

  5+ ansCandidates need a bachelor's degree in electrical or computer engineering or equivalent, and 5 to 10+ years of direct digital IC design experience with a track record of working products. Experience with CAD tools, scripting in Python or TCL, and DSP, microcontrollers or FPGA is an asset.

  VHDL, Python, TCL, FPGA, C

• 1 mois

  Project Engineering Management, Principal Engineer - 18617

  Mississauga, ON

  S

  Synopsys

  8+ ansCandidates need an engineering or applied science degree (or equivalent) and 8+ years of semiconductor experience. Strong project management skills, customer communication experience, and knowledge of SOC, ASIC, Silicon IP, PCIe and Ethernet are expected.

  Linux

  1 mois

  ASIC Digital Design, Principal Engineer-18731

  Mississauga, ON

  S

  Synopsys

  Candidates need extensive mixed-signal ASIC or IP verification experience, strong PCIe and PCIe PHY knowledge, and hands-on SystemVerilog and UVM skills. Strong debugging and mentoring abilities are also required.

  SystemVerilog, UVM

  1 mois

  Analog Design, Sr Staff Engineer - 18597

  Ottawa, ON

  S

  Synopsys

  7+ ansCandidates need an engineering or applied science degree and 7 to 12 years of semiconductor, Silicon IP or SoC experience. Strong project management, customer communication and cross-functional leadership skills are required, along with familiarity with Linux environments.

  Linux

  1 mois

  Project Engineering Management, Principal Engineer

  Mississauga, ON

  S

  Synopsys

  10+ ansCandidates need an engineering degree or equivalent experience, 10+ years of customer-facing project management, and familiarity with mixed-signal IP, SoC or ASIC development. Strong communication, MS Project, Jira, UNIX/Linux and quality management system knowledge are also required.

  MS Project, Jira, UNIX, Linux

  1 mois

  ASIC Digital Verification, Sr. Manager

  Mississauga, ON

  S

  Synopsys

  15+ ansCandidates need a BS or MS in EE, EC or VLSI with 15+ years of IP or SoC verification experience, and strong team leadership. They must know Verilog, SystemVerilog and UVM, and Perl or Python automation. PCIe and Ethernet knowledge is an asset.

  Verilog, SystemVerilog, UVM, Perl, Python

• 1 mois

  Sr. Manager, Physical Design Engineering, Annapurna Labs

  Toronto, ON

  Temps plein

  AD

  Amazon Development Centre Canada ULC

  10+ ans5+ gestionAmazon Development Centre Canada needs 5+ years leading physical design teams of 8+ engineers and 10+ years of hands-on ASIC/SoC physical design across advanced nodes. Candidates must master both Synopsys and Cadence EDA tools, advanced STA and power integrity, and hierarchical flows for very large SoCs.

  Synopsys Fusion Compiler, ICC2, PrimeTime, StarRC, RedHawk-SC, Cadence Innovus

  1 mois

  Design Verification Engineer, Annapurna Labs

  Toronto, ON

  Temps plein

  AD

  Amazon Development Centre Canada ULC

  4+ ansCandidates need a bachelor's degree in electrical engineering or a related field and at least 4 years of design verification experience using constrained-random simulation such as UVM. Strong debugging skills across IP, SoC and full-system levels are required.

  UVM, Python, Perl, C++

  1 mois

  Design Verification Engineer - technical lead, Annapurna Labs

  Toronto, ON

  Temps plein

  AD

  Amazon Development Centre Canada ULC

  8+ ansCandidates need a bachelor's degree in electrical engineering or a related field and 8+ years of constrained-random verification experience (such as UVM), including testbench development. Experience across IP, SoC and full-system verification, plus formal, emulation or scripting skills, is highly desired.

  UVM, formal verification tools, emulation platforms, Python, Perl

• 1 mois

  Intermediate Embedded Software Engineer – BSP and Bootloaders

  Kanata, ON

  76,20–79,66 $/hContrat

  

  Randstad Canada

  4+ ansCandidates need a bachelor's degree in a technical field, 4+ years of BSP and bootloader work on Linux or QNX, and 2+ full target board bring-ups. Strong low-level C, ARM Cortex knowledge, and lab debugging with JTAG, oscilloscopes and logic analyzers are required.

  JTAG debugger, oscilloscope, logic analyzer, Git, SVN

  1 mois

  Sr. Embedded Linus Dev - Hybrid

  Mississauga, ON

  110k–145k $/anTemps plein

  

  Randstad Canada

  5+ ansCandidates need 5+ years of embedded Linux development, with deep audio or multimedia experience. Expert knowledge of ALSA SoC, Yocto/BitBake, GStreamer or PipeWire, and kernel C programming is required.

  Yocto, BitBake, PipeWire, GStreamer, ftrace, perf

• 1 mois

  DFT Engineer, Principal

  Toronto, ON

  Sur place

  

  Qualcomm Canada ULC

  8+ ansCandidates need 10+ years of SoC experience in RTL, DFT or front-end roles, and extensive use of Siemens, Synopsys and Cadence DFT tools. Strong Verilog, VHDL and SystemVerilog skills, knowledge of JTAG, iJTAG and BIST standards, and TCL or Python scripting are expected.

  Siemens DFT tools, Cadence DFT tools, Verilog, VHDL, SystemVerilog, TCL

  1 mois

  DFT Engineer (Senior to Staff level)

  Toronto, ON

  Sur place

  

  Qualcomm Canada ULC

  10+ ansCandidates need a bachelor's degree in an engineering or computer science field and 10+ years of SoC design experience in RTL, DFT or front-end work. They need strong knowledge of DFT tools, Verilog, VHDL and SystemVerilog, and standards such as JTAG, iJTAG and BIST.

  Siemens DFT tools, Cadence DFT tools, Verilog, VHDL, SystemVerilog, TCL

10 entreprises