Senior Digital ASIC Designer
Montréal, QCTemps plein
SM
SPARK Microsystems
8+ ansCandidates need a Bachelor's or Master's in Electrical Engineering or equivalent, 8+ years of digital ASIC design experience with 4+ in a senior role, and strong skills in digital logic, Verilog, SystemVerilog or VHDL, and synthesis and timing analysis tools.
Verilog, SystemVerilog, VHDL, synthesis tools, STA tools, protocol analyzers