Emplois “UVM” au Canada – Page 3

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• 26j

  Senior Design Verification Engineer

  Toronto, ON

  T

  Talentlab

  3+ ansTalentlab needs candidates with 3 to 8 years of design verification experience and strong SystemVerilog and UVM skills. Experience with SerDes, DSP or mixed-signal designs is needed, and Ethernet and PCIe knowledge is a strong plus.

  SystemVerilog, UVM, Python, Perl, C/C++, GNU Make

  26j

  Senior ASIC Verification Engineer

  Ottawa, ON

  Hybride

  T

  Talentlab

  Candidates need an engineering degree, proven digital verification experience, and knowledge of formal verification and functional coverage. They should also be proficient in a programming language such as Python or C/C++ and be based in Ottawa.

  SystemVerilog, UVM, Python, C++, SystemC, Make

• 27j

  Design Verification Engineer

  Markham, ON

  Temps plein

  AI

  AMD, Inc.

  AMD asks for advanced ASIC functional verification experience and hands-on work on multiple projects or tapeouts. Candidates need Verilog, SystemVerilog, UVM, scripting skills, and a Bachelor's or Master's in Computer or Electrical Engineering.

  Verilog, UVM, Makefiles, Perl, Python, Ruby

  27j

  Silicon Design Engineer

  Markham, ON

  Temps plein

  AI

  AMD, Inc.

  Candidates need a bachelor's degree in electrical or computer engineering, with a master's or PhD preferred. AMD wants hands-on ASIC firmware and hardware verification experience with UVM, SystemVerilog, C/C++ and bus protocols such as AXI and AHB.

  UVM, Verilog, C-DPI, Python, Perl, Make

  27j

  Verification Engineer

  Markham, ON

  Temps plein

  AI

  AMD, Inc.

  Candidates need strong SystemVerilog and UVM skills, experience with ASIC or SoC verification, and familiarity with constrained-random, coverage-driven and formal verification. A Bachelor's or Master's in computer or electrical engineering is required.

  UVM, Synopsys VCS, Cadence IES, Cadence IEV, Jasper, Synopsys VC-Formal

  27j

  SoC Design Lead, Microarchitecture and Design Methodology

  Markham, ON

  Temps plein

  AI

  AMD, Inc.

  Candidates need a strong foundation in computer architecture and digital design, along with static timing analysis, clock and power optimization knowledge. Experience with Verilog or SystemVerilog, and UVM preferred, plus strong communication and teamwork skills.

  Verilog, SystemVerilog, UVM

  27j

  Silicon Design Verification Engineer

  Markham, ON

  Temps plein

  AI

  AMD, Inc.

  Candidates need a Bachelor's or Master's in Computer or Electrical Engineering, knowledge of digital design and computer architecture, and hands-on SystemVerilog, UVM and C++ or Python experience. Prior verification work and PCIe or AXI protocol knowledge are assets.

  UVM, C++, Python, Formal verification tools

  27j

  Design Verification Lead

  Markham, ON

  Temps plein

  AI

  AMD, Inc.

  Candidates need a bachelor's or master's degree in electrical or computer engineering, computer science or a related field, plus UVM and SystemVerilog experience and knowledge of high-speed protocols such as PCIe, CXL or Ethernet. Scripting in Python or Perl and technical leadership skills are also needed.

  SystemVerilog, Verilog, UVM, Python, Perl

• 27j

  Design Verification Engineer Intern (Toronto)

  Toronto, ON

  AL

  Astera Labs Early Career - North America 2027

  Candidates need to be pursuing a bachelor's or master's degree in electrical, computer engineering or computer science. They need coding skills in SystemVerilog, C/C++ or Python, Linux and Git familiarity, and strong debugging ability.

  VCS, Verdi, DVE

• 28j

  Design Verification Lead

  Markham, ON

  Temps plein

  AM

  Advanced Micro Devices, Inc

  Candidates need a Bachelor's or Master's degree in an electrical, computer or related engineering field, strong UVM and SystemVerilog skills, and experience verifying high-speed protocols such as PCIe, CXL or Ethernet. Technical leadership, mentoring and scripting in Python or Perl are preferred.

  SystemVerilog, Verilog, UVM, Python, Perl

  1 mois

  Design Verification Engineer

  Markham, ON

  Temps plein

  AM

  Advanced Micro Devices, Inc

  Candidates need hands-on hardware verification experience across multiple projects or tapeouts, with SystemVerilog, UVM, Verilog and scripting skills. A Bachelor's or Master's in Computer or Electrical Engineering is expected.

  UVM, Verilog, Makefiles, Perl, Python, Ruby

  1 mois

  Verification Engineer

  Markham, ON

  Temps plein

  AM

  Advanced Micro Devices, Inc

  Candidates need strong SystemVerilog and UVM skills, solid ASIC/SoC verification experience, and familiarity with constrained-random, coverage-driven and formal (SVA) methods. A bachelor's or master's in computer or electrical engineering is required.

  Synopsys VCS, Cadence IES, Cadence IEV, Jasper, VC-Formal, Magellan

  1 mois

  Summer 2027 Long Term Hardware Design Verification Engineering Intern/Co-Op

  Markham, ON

  AM

  Advanced Micro Devices, Inc

  Candidates need to be enrolled in a Canada-based university Bachelor's program in electrical engineering, computer science, computer engineering or a related field. Experience with C++, Python, Perl, UVM, Verilog or SystemVerilog, digital systems, and Linux or Windows debugging is an asset.

  Verilog, UVM, Perl, Python, MySQL, PHP

  1 mois

  Short Term 2027 Hardware Design Verification Engineering Intern/Co-Op

  Vancouver, BC

  AM

  Advanced Micro Devices, Inc

  Candidates need to be enrolled in a Canadian university Bachelor's program in electrical engineering, computer science, computer engineering or a related field. Programming in C++, Python, Perl or Shell, and knowledge of Verilog, SystemVerilog and digital logic design, are strongly encouraged.

  Verilog, UVM, Perl, Python, MySQL, PHP

  1 mois

  Summer 2027 Long Term ASIC Verification Engineering Intern/ Co-Op

  Ottawa, ON

  AM

  Advanced Micro Devices, Inc

  Candidates need to be 3rd or 4th year Computer Engineering or Computer Science students with digital design knowledge, object-oriented coding skills, and experience with SystemVerilog, C or C++. Experience with AI tools is required, and Python, Perl or other scripting languages are an asset.

  SystemVerilog, UVM, C++, Python, Perl

  1 mois

  Short Term 2027 Hardware Design Verification Engineering Intern/Co-Op

  Markham, ON

  AM

  Advanced Micro Devices, Inc

  Candidates need current enrolment in a Canadian university Bachelor's program in electrical engineering, computer science, computer engineering or a related field. Programming in Python, Perl or C++, and familiarity with Verilog, SystemVerilog and digital logic design are strongly preferred.

  Verilog, UVM, Perl, Python, MySQL, PHP

  1 mois

  Silicon Design Verification Engineer

  Markham, ON

  Temps plein

  AM

  Advanced Micro Devices, Inc

  Candidates need a Bachelor's or Master's in Computer or Electrical Engineering, plus knowledge of digital logic and computer architecture. Experience with SystemVerilog, UVM, C++ and Python, and protocols such as PCIe or AXI, is preferred.

  UVM, C++, Python, SVA formal tools

• 1 mois

  Principal Digital Verification Engineer

  Nepean, ON

  S

  Synopsys

  12+ ansSynopsys candidates need 12+ years of verification experience with a BSc, 10+ years with an MSc, or 8+ years with a PhD. They need deep SystemVerilog and UVM skills, simulation and waveform debugging, C knowledge, assertion-based verification, and Linux scripting. Experience with LPDDR5/5X or LPDDR6 and emulation platforms is a plus.

  SystemVerilog, UVM, waveform debugger, Linux, source control, emulation platform

  1 mois

  ASIC Digital Design, Principal Engineer-18731

  Mississauga, ON

  S

  Synopsys

  Candidates need extensive mixed-signal ASIC or IP verification experience, strong PCIe and PCIe PHY knowledge, and hands-on SystemVerilog and UVM skills. Strong debugging and mentoring abilities are also required.

  SystemVerilog, UVM

  1 mois

  ASIC Digital Verification, Sr. Manager

  Mississauga, ON

  S

  Synopsys

  15+ ansCandidates need a BS or MS in EE, EC or VLSI with 15+ years of IP or SoC verification experience, and strong team leadership. They must know Verilog, SystemVerilog and UVM, and Perl or Python automation. PCIe and Ethernet knowledge is an asset.

  Verilog, SystemVerilog, UVM, Perl, Python

• 1 mois

  Staff ASIC Verification Engineer, Low Power AI

  Markham, ON

  Sur place

  

  Qualcomm Canada ULC

  4+ ansQualcomm Canada ULC needs candidates with a relevant degree and 4+ years of ASIC work (3+ with a master's, 2+ with a PhD). Expert knowledge of Verilog, VHDL and SystemVerilog UVM is required, plus solid C skills.

  SystemVerilog, UVM, Verilog, VHDL, SystemC, Perl

• 1 mois

  Design Verification Engineer, Annapurna Labs

  Toronto, ON

  Temps plein

  AD

  Amazon Development Centre Canada ULC

  4+ ansCandidates need a bachelor's degree in electrical engineering or a related field and at least 4 years of design verification experience using constrained-random simulation such as UVM. Strong debugging skills across IP, SoC and full-system levels are required.

  UVM, Python, Perl, C++

  1 mois

  Design Verification Engineer - technical lead, Annapurna Labs

  Toronto, ON

  Temps plein

  AD

  Amazon Development Centre Canada ULC

  8+ ansCandidates need a bachelor's degree in electrical engineering or a related field and 8+ years of constrained-random verification experience (such as UVM), including testbench development. Experience across IP, SoC and full-system verification, plus formal, emulation or scripting skills, is highly desired.

  UVM, formal verification tools, emulation platforms, Python, Perl

• 1 mois

  Principal Design Verification Engineer

  Toronto, ON

  

  indie

  7+ ansCandidates need a BSEE, BSCE or BSCS and 7+ years of design verification experience. Required skills include constrained random verification with SystemVerilog and UVM, coverage-driven verification, and strong programming in C/C++ with Python, Tcl or Perl scripting.

  SystemVerilog, UVM, C, C++, Python, Tcl

8 entreprises