Senior Director, Technology
Ottawa, ONQualcomm Canada ULC
10+ ansCandidates need a bachelor's in electrical engineering with 10 years of ASIC or IP development experience, or a master's with 8 years. They also need hands-on knowledge of Ethernet, UALink and OTN, HDL languages, SystemVerilog UVM and verification methods.
SystemVerilog, Verilog, VHDL, UVM, Unix/Linux, SVN
FY27 Intern - Softip Engineering Co-Op - Canada (4 months)
Ottawa, ONQualcomm Canada ULC
1+ ansCandidates need to be enrolled in a bachelor's or master's program in electrical, computer or related engineering, with scripting experience in Python, Perl, TCL or Unix/Linux shell and experience with source code revision systems.
Verilog, SystemVerilog, UVM, VHDL, SVN, CVS
Analog Engineer, Principal
Toronto, ONQualcomm Canada ULC
8+ ansCandidates need a Master's or PhD in electrical engineering (or a Bachelor's with 2+ years of analog or mixed-signal design), plus 8+ years of ASIC design or related work and silicon-proven analog circuit experience in advanced CMOS. Strong skills in Cadence, SPICE, MATLAB or Verilog-A are expected.
Cadence ADE, MATLAB, SPICE, Verilog-A
FY27 Intern - Firmware/Embedded Software Engineering Internship - Canada (12 or 16 months)
Toronto, ONQualcomm Canada ULC
1+ ansCandidates need to be enrolled in a bachelor's degree in electrical or computer engineering, engineering science or computer science, with at least one year of academic programming experience in C, C++ or Python. Strong debugging, problem-solving and teamwork skills are needed, and availability must match the 12- or 16-month internship dates.
Git, Linux, FPGA, Verilog, SystemVerilog, GitHub Actions
Sr ASIC Design Verification Engineer, Low Power AI
Markham, ONQualcomm Canada ULC
2+ ansQualcomm Canada ULC needs candidates with a bachelor's, master's or PhD and 2 to 4+ years of ASIC work, depending on degree. Expert skill in Verilog, SystemVerilog, UVM and C, plus a deep understanding of ASIC/VLSI concepts, is required.
SystemVerilog, UVM, Verilog, VHDL, SystemC, Perl
FY27 Intern - Display IP Engineering Internship - Canada (16 months)
Markham, ONQualcomm Canada ULC
1+ ansCandidates need to be enrolled in a bachelor's program in electrical, computer or engineering science, or a related field, with a graduation date of November 2028 or later. They need programming experience in C, C++ or Python, knowledge of RTL, Verilog or SystemVerilog and digital design, and good communication and teamwork skills.
Verilog, VHDL, Perl, Python, TCL, GNU Make
Staff Verification Engineer, Compute Subsystems
Markham, ONQualcomm Canada ULC
5+ ansCandidates need a bachelor's, master's, or PhD in engineering or science with several years of ASIC design or verification experience, plus strong UVM and SystemVerilog skills, bus protocol knowledge, and scripting in Perl or Python.
UVM, Perl, Python, C
FY27 Intern - Edge AI and Display Hardware Architecture Development Engineering Internship - Canada (16 months)
Markham, ONQualcomm Canada ULC
Qualcomm Canada ULC needs candidates enrolled in an engineering or computer science bachelor's program, available May/June 2027 to August/September 2028 and graduating November 2028 or later. Strong analytical skills, programming in C/C++ or Python, and HW modeling and simulation experience are required.
Verilog, VHDL, C/C++, Python, HW simulation tools, HW CAD tools
FY27 Intern - Camera HW ASIC Verification Intern - Canada (12 or 16 months)
Vancouver, BCQualcomm Canada ULC
1+ ansCandidates need Verilog or SystemVerilog skills, ASIC design verification experience and scripting ability. Study toward a bachelor's degree in electrical, computer or a related engineering field is required.
Verilog, UVM, Python, Perl
FY27 Intern - Camera Design Engineering Internship - Canada (12 or 16 months)
Vancouver, BCQualcomm Canada ULC
1+ ansCandidates need to be enrolled toward a bachelor's degree in electrical, computer or a related engineering or science field. They need experience in Tcl, Perl, Python and SystemVerilog, plus academic or project VLSI experience as an asset.
Verilog, Tcl, Perl, Python, EDA tools
Camera Design Engineer
Vancouver, BCQualcomm Canada ULC
3+ ansCandidates need a bachelor's, master's or PhD in a computer, electrical or related engineering field, with 4 to 2 years of hardware or related experience depending on degree. Verilog or VHDL RTL design, design verification and bus protocol experience are key.
Verilog, VHDL, TCL, Perl, Python