Emplois “tcl” au Canada – Page 3

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• 11j

  ASIC Engineer Intern

  Ottawa, ON

  25,50–35 $/hTemps plein

  CC

  Ciena Canada ULC

  Candidates need programming experience in Java, Python, TCL, Skill/Ocean or SystemVerilog, and familiarity with Linux. Experience with ASIC or FPGA work, debugging skills and Agile, JIRA, Confluence or Git are assets.

  SystemVerilog, UVM, Python, TCL, Skill/Ocean, Java

  13j

  Embedded Software Engineer – Co-op Winter 2027

  Ottawa, ON

  25–34 $/hTemps plein

  CC

  Ciena Canada ULC

  Candidates need to be enrolled in a bachelor's or master's program in computer or electrical engineering, computer science or a similar discipline. Experience with C or C++ is required, and embedded systems or telecom experience is an asset.

  Git, Bitbucket, Gerrit, Jira, gdb, Google Test

• 12j

  Engineering Student - FPGA Designer - Winter 2027

  Sainte-Anne-de-Bellevue, QC

  Temps plein

  

  MDA

  MDA Space needs candidates who have completed third year of an electrical or computer engineering degree with at least 3.2/4.0. Experience with VHDL, Verilog, Python or C/C++ and tools like Linux, Git and Jira is an asset, as is French and English.

  VHDL, Verilog, SystemVerilog, Tcl, Python, C/C++

  12j

  Engineering Student - FPGA Verification - Winter 2027

  Sainte-Anne-de-Bellevue, QC

  Temps plein

  

  MDA

  Candidates need completion of a third year of an electrical or computer engineering bachelor's degree with a 3.2/4.0 minimum GPA. They need a desire to learn, initiative, and a collaborative attitude, plus security clearance eligibility.

  SystemVerilog, VHDL, Verilog, Tcl, Python, C/C++

• 12j

  FPGA Team Lead (Hybrid)

  Burnaby, BC

  

  Kardium Inc.

  5+ ans1+ gestionCandidates need a bachelor's degree or higher in electrical or computer engineering, at least 5 years of hands-on FPGA design and verification, and 1-2 years leading or mentoring engineers. Strong VHDL skills and experience with Xilinx/AMD tools are required, and medical device quality standards are an asset.

  Vivado, Vitis, Altium Designer, ModelSim, Questa, Active-HDL

  12j

  Senior FPGA Engineer (Hybrid)

  Burnaby, BC

  

  Kardium Inc.

  5+ ansCandidates need a bachelor's degree or higher in an engineering field and at least 5 years of FPGA development and verification experience. Strong VHDL, Vivado and Active-HDL skills, plus excellent communication, are required.

  Vivado, Active-HDL, Logic analyzer, Oscilloscope, Git

• 12j

  Lead Emulation Test Engineer

  Télétravail au Canada

  TélétravailTemps plein

  

  Positron AI

  8+ ansCandidates need 8+ years in ASIC emulation or verification, including large Palladium installations, and a BS or MS in electrical engineering, computer engineering or computer science. Strong skills in SystemVerilog, Verilog, C/C++, Python, Tcl and Bash are required, along with knowledge of PCIe, DDR and AXI protocols.

  Cadence Palladium, Verdi, SimVision

• 18j

  Physical Design Engineering Director

  Toronto, ON

  

  Astera Labs: Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions.

  15+ ans5+ gestionCandidates need a bachelor's degree in an electrical or computer engineering field, with 15+ years of physical design experience on advanced nodes and 5+ years leading teams. Hands-on skill with Cadence Innovus or Synopsys tools and scripting in Tcl, Python or Perl is required.

  Cadence Innovus, Synopsys Fusion Compiler, ICC2, Tcl, Python, Perl

• 18j

  RTL Design Engineer

  Markham, ON

  Temps plein

  AM

  Advanced Micro Devices, Inc

  Candidates need a Bachelor's or Master's degree in an electrical, computer or related engineering field, strong Verilog and SystemVerilog skills, scripting experience, and knowledge of AXI, AHB and AMBA protocols. Experience with ASIC design flows and processor or security subsystems is preferred.

  Verilog, SystemVerilog, Python, Tcl, Perl, Ruby

  20j

  RTL Design Engineer

  Markham, ON

  Temps plein

  AM

  Advanced Micro Devices, Inc

  Candidates need a bachelor's or master's degree in electrical or computer engineering or a related field, with strong Verilog and SystemVerilog skills and knowledge of CPU and embedded processor architectures. Experience with AXI, AHB, AMBA and ASIC design tools is preferred.

  Verilog, SystemVerilog, Python, Tcl, Perl, Ruby

  21j

  Sr. Staff Physical Design Engineer

  Vancouver, BC

  Temps plein

  AM

  Advanced Micro Devices, Inc

  AMD needs candidates with strong physical design experience for high-performance semiconductors, including timing closure and signoff. Candidates should know tools such as ICC2, Fusion Compiler, PrimeTime, Calibre and Innovus, and be proficient in Python and TCL.

  Synopsys ICC2, Synopsys ICC, Fusion Compiler, PrimeTime, StarRC, Mentor Graphics Calibre

  22j

  Silicon Design Engineer (1 year contract)

  Markham, ON

  Temporaire

  AM

  Advanced Micro Devices, Inc

  Candidates need a bachelor's or master's degree in computer or electrical engineering, scripting skills in Perl, Python or TCL, and knowledge of digital circuits and VLSI. Strong problem-solving and communication skills are preferred.

  Perl, Python, TCL, C++, SQL

• 18j

  FPGA Digital Design Engineer (6+ month Contract)

  Toronto, ON

  TélétravailTemps plein, Contrat

  

  Kepler Communications

  5+ ansCandidates need a bachelor's degree in computer or electrical engineering, 5+ years of FPGA/RTL design experience, and skill in Verilog, SystemVerilog or VHDL. They also need Xilinx Zynq or UltraScale experience, timing and clock domain crossing knowledge, and scripting skills.

  Vivado, Quartus, ModelSim, Python, Tcl

• 18j

  RTL Design Engineer

  Markham, ON

  Temps plein

  AI

  AMD, Inc.

  AMD needs candidates with a Bachelor's or Master's degree in an electrical, computer or related engineering field, with Master's preferred. Strong skills in Verilog, SystemVerilog and scripting such as Python, Tcl or Perl are expected, along with knowledge of processor subsystems and ASIC design flows.

  Verilog, SystemVerilog, Python, Tcl, Perl, Ruby

  20j

  RTL Design Engineer

  Markham, ON

  Temps plein

  AI

  AMD, Inc.

  Candidates need a strong background in RTL design, Verilog and SystemVerilog, and scripting in Python, Tcl, Perl, Ruby, or Make. Experience with AXI, AHB, AMBA protocols, ASIC design tools, and a Bachelor's or Master's degree in electrical or computer engineering are expected.

  Verilog, SystemVerilog, C-DPI, FPGA, ASIC simulation and synthesis tools

  22j

  Sr. Staff Physical Design Engineer

  Vancouver, BC

  Temps plein

  AI

  AMD, Inc.

  Candidates need strong experience in high-performance physical design, timing closure and physical signoff, plus proficiency in Python and TCL for flow automation. Experience leading engineers and an electronics or electrical engineering background are preferred.

  Synopsys ICC2, Fusion Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache RedHawk

  22j

  Silicon Design Engineer (1 year contract)

  Markham, ON

  Temporaire

  AI

  AMD, Inc.

  Candidates need a bachelor's or master's in computer or electrical engineering. Preferred experience includes scripting in Perl, Python or Shell, C++, SQL, VLSI knowledge and AI/ML applications.

  Perl, Python, TCL, C++, SQL

  23j

  Validation Lead-Fuse/SoC

  Markham, ON

  Temps plein

  AI

  AMD, Inc.

  Candidates need a bachelor's or master's in electrical or computer engineering, semiconductor and digital circuit knowledge, and silicon bring-up experience. Experience with eFuse or fuse repair, and scripting in Python, Perl or Tcl, is required.

  Python, Perl, Tcl, SQL, EDA tools, ATE platforms

• 20j

  Principal Analog Design Engineer-19318

  Markham, ON

  S

  Synopsys

  6+ ansCandidates need a PhD with 6+ years or a Master's with 8+ years of analog and mixed-signal IC design experience, including FinFET circuit design. Strong transistor-level CMOS and SPICE simulation skills are required.

  Spectre, HSPICE, Verilog-A, schematic entry tools, Python, Perl

  20j

  R&D Engineering, Staff Engineer

  Ottawa, ON

  S

  Synopsys

  7+ ansCandidates need 7-8+ years of experience with a bachelor's degree, 5-6+ with a master's, or 3-4+ with a PhD, in an engineering or computer science field. They need strong skills in CAD or simulation infrastructure, scripting in Python, Tcl or Shell, and Linux environments.

  Synopsys EDA design suite, Linux, Python, Tcl, Shell

  21j

  Analog Design, Architect - 18618

  Mississauga, ON

  S

  Synopsys

  10+ ansCandidates need a PhD with 10+ years or MSc with 12+ years of SerDes or high-speed analog design experience. Synopsys expects silicon-proven TX, RX and clock circuit work, transistor-level CMOS and FinFET layout skills, and some leadership of small teams.

  SPICE, Verilog-A, TCL, Perl, C, Python

  25j

  CAD Software Engineer, Principal-18736

  Nepean, ON

  S

  Synopsys

  10+ ansSynopsys needs candidates with an MS or PhD in Computer Science or Electrical Engineering and at least 10 years of industry experience. They should be strong in Python, Perl, TCL, UNIX/Linux, Git, and Perforce, and have hands-on experience with Custom Compiler/Virtuoso.

  Custom Compiler, Virtuoso, Git, Perforce, UNIX, Linux

• 20j

  Embedded Software Designer

  Télétravail au Canada

  100k–150k $/anTélétravailTemps plein

  

  Fidus Systems: Founded in 2001, Fidus Systems is a premier electronic system design and development company with specialized expertise in FPGA design, embedded…

  8+ ans2+ gestionFidus Systems needs candidates with an engineering or computer science degree, at least 8 years of BSP-level embedded software work and 2 years as a technical lead. They should know embedded Linux, FPGA SoCs, C, C++ and scripting, and be fluent in English.

  oscilloscope, logic analyzer, Yocto, PetaLinux, u-boot

• 20j

  Senior ASIC Design Engineer - DSP/Analog/SerDes

  Ottawa, ON

  CC

  Celero Communications, Inc.

  10+ ansCandidates need a master's or PhD in electrical or computer engineering, 10+ years of digital ASIC design, and strong Verilog or SystemVerilog skills. Knowledge of DSP, high-speed SerDes, mixed-signal or optical communications is also required.

  Verilog, SystemVerilog, Python, Tcl, MATLAB, UVM

11 entreprises