CPU Micro-Architect / RTL (Lead & IC Engineers)
CanadaNUVACORE
7+ ansCandidates need a BS or MS with 15+ years of CPU design experience for leads or 7+ years for individual contributors. They must know Verilog, simulation and logic and physical design, and understand RISC-V, ARM64 or x86 ISAs.
Verilog, AI tools for RTL coding, simulation tools, emulation
CPU Architecture Verification Engineer
Markham, ONNUVACORE
4+ ansCandidates need a degree in electrical or computer engineering, computer science or equivalent experience, plus 4+ years (Senior) or 15+ years (Principal) of design verification. They need strong CPU architecture knowledge, one modern ISA (x86, ARM or RISC-V), and skill in C/C++/Rust or SystemVerilog with Python.
SystemVerilog, Python, Perl, FPGA
Compiler and ToolChain Engineer
CanadaNUVACORE
15+ ansCandidates need 15+ years of professional compiler internals experience in LLVM and/or GCC, strong backend knowledge, and low-level programming on x86, ARM or RISC-V. NUVACORE also expects experience debugging complex systems, performance analysis of JIT and multi-language environments, and strong communication skills.
LLVM, GCC, binutils, QEMU