Design Verification Engineer, Annapurna Labs
Toronto, ONTemps plein
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Amazon Development Centre Canada ULC
4+ ansCandidates need a bachelor's degree in electrical engineering or a related field and at least 4 years of design verification experience using constrained-random simulation such as UVM. Strong debugging skills across IP, SoC and full-system levels are required.
UVM, Python, Perl, C++
Design Verification Engineer - technical lead, Annapurna Labs
Toronto, ONTemps plein
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Amazon Development Centre Canada ULC
8+ ansCandidates need a bachelor's degree in electrical engineering or a related field and 8+ years of constrained-random verification experience (such as UVM), including testbench development. Experience across IP, SoC and full-system verification, plus formal, emulation or scripting skills, is highly desired.
UVM, formal verification tools, emulation platforms, Python, Perl