Static Timing Analysis (STA) Engineer
Toronto, ONTemps plein
A
Altera
6+ ansCandidates need 6+ years of static timing analysis experience on ASIC or FPGA designs, plus a strong grasp of STA fundamentals and tools such as PrimeTime. A bachelor's or master's degree in electrical or computer engineering, with RTL design knowledge, is required.
PrimeTime, Verilog, SystemVerilog, Tcl, Python
FPGA Compiler (Placer) Engineer
Toronto, ONTemps plein
A
Altera
6+ ansCandidates need 6+ years in FPGA or ASIC CAD, EDA tools or physical design, strong algorithms skills, and C/C++ experience. A bachelor's or master's in electrical, computer engineering or computer science is required.
Quartus, Vivado, C++, Python, Tcl