RTL Design Engineer
Markham, ONTemps plein
AI
AMD, Inc.
Candidates need a strong background in RTL design, Verilog and SystemVerilog, and scripting in Python, Tcl, Perl, Ruby, or Make. Experience with AXI, AHB, AMBA protocols, ASIC design tools, and a Bachelor's or Master's degree in electrical or computer engineering are expected.
Verilog, SystemVerilog, C-DPI, FPGA, ASIC simulation and synthesis tools