FPGA Design Engineer
Nepean, ON65–85 $/hContrat
Actalent: Actalent is an operating company of Allegis Group, the global leader in talent solutions.
5+ ansCandidates need 5+ years of ASIC or FPGA design experience, strong SystemVerilog skills, and hands-on Cadence simulation and design debug experience. Experience with synthesis, timing analysis and simulation frameworks is also required.
Xilinx Vivado, Cadence simulation tools, SystemVerilog, VHDL