FPGA Design Engineer
Ottawa, ON65–85 $/hContrat
Actalent: Actalent is an operating company of Allegis Group, the global leader in talent solutions.
5+ ansCandidates need 5+ years of ASIC/FPGA design experience, strong SystemVerilog skills, hands-on Cadence simulation experience, and practical debug and timing analysis skills. VHDL, Xilinx Vivado, Python, C/C++, DSP and high-speed interface experience are assets.
SystemVerilog, Xilinx, Vivado, Cadence simulation tools, Python, C
Ingénieur ÉLectrique/Hardware // Electrical / Hardware Engineer
Montréal, QC35–45 $/hContrat
Actalent: Actalent is an operating company of Allegis Group, the global leader in talent solutions.
3+ ans3 ans d'expérience avec Altium; 1 an d'expérience avec Git/GitHub; 3 ans de conception ou test de matériel/PCB
Altium, Git, GitHub