Analog Design, Manager - 18463
Kanata, ONSynopsys
8+ ans2+ gestionCandidates need an M.A.Sc. with 8+ years or a PhD with 6+ years of analog or mixed-signal IC design experience, plus 2+ years of people management. They must have deep Multi-Gbps SerDes expertise, transistor-level design skills, and experience with SPICE, Verilog-A and layout.
SPICE, Verilog-A, Industry-standard simulation tools
Principal SI/PI Engineer - 18619
Mississauga, ONSynopsys
12+ ansCandidates need a bachelor's degree (master's or PhD preferred) in electrical engineering and 12+ years of high-speed SI/PI experience on SerDes links. They also need strong skills in simulation tools, lab measurement and scripting, plus proven technical leadership.
HSPICE, Keysight ADS, SystemVue, Ansys HFSS, SIwave, AEDT
Principal Digital Verification Engineer
Nepean, ONSynopsys
12+ ansSynopsys candidates need 12+ years of verification experience with a BSc, 10+ years with an MSc, or 8+ years with a PhD. They need deep SystemVerilog and UVM skills, simulation and waveform debugging, C knowledge, assertion-based verification, and Linux scripting. Experience with LPDDR5/5X or LPDDR6 and emulation platforms is a plus.
SystemVerilog, UVM, waveform debugger, Linux, source control, emulation platform
Project Engineering Management, Principal Engineer - 18617
Mississauga, ONSynopsys
8+ ansCandidates need an engineering or applied science degree (or equivalent) and 8+ years of semiconductor experience. Strong project management skills, customer communication experience, and knowledge of SOC, ASIC, Silicon IP, PCIe and Ethernet are expected.
Linux
Silicon Validation Engineer
Mississauga, ONSynopsys
6+ ansCandidates need a Master's in electrical or electronics engineering with 6+ years of post-silicon validation experience, or a Bachelor's with 7+ years. Hands-on lab skill with BERTs, oscilloscopes, VNAs and TDRs, plus MATLAB and Python, is required.
BERT, real-time oscilloscope, sampling oscilloscope, VNA, TDR, MATLAB
Senior Staff Hardware Validation Engineer
Mississauga, ONSynopsys
6+ ansSynopsys needs a bachelor's degree in electrical or electronic engineering with 8 years of relevant experience, or a master's with 6 years. Candidates need lab test equipment experience, PCB fabrication house experience and skill running PI and SI simulations.
HFSS, high-speed scopes, power meters, IR cameras, FPGA development tools, Verilog HDL
Silicon Validation Software Engineer (Sr Staff)
Mississauga, ONSynopsys
8+ ansCandidates need 8+ years of software development in silicon validation or hardware test (or a master's with 6+ years), strong Python skills, and experience deploying validation tools. Git or GitLab, hardware debugging across the stack and lab experience are also needed.
Python, Git, GitLab, JTAG, I2C, SPI
Hardware Validation Senior Engineering Manager
Mississauga, ONSynopsys
10+ ans3+ gestionCandidates need a bachelor's degree in electrical or electronics engineering with 10+ years of experience, or a master's with 8+ years. They must have 3+ years managing engineers, full PCB design experience, and skill with signal simulation tools such as HFSS or ADS.
HFSS, ADS, oscilloscope, spectrum analyzer, power meter, thermal camera
Silicon Validation/Characterization Engineer - 18757
Nepean, ONSynopsys
3+ ansCandidates need a Bachelor's or Master's in electrical or computer engineering or a related field, plus 3+ years of semiconductor validation or characterization experience. They need knowledge of DDR/LPDDR/HBM protocols and lab instruments, and skill in Python or C/C++ scripting.
oscilloscope, logic analyzer, power analyzer, SMU, pattern generator, Automated Test Equipment (ATE)
Analog Design, Sr Staff Engineer - 18597
Ottawa, ONSynopsys
7+ ansCandidates need an engineering or applied science degree and 7 to 12 years of semiconductor, Silicon IP or SoC experience. Strong project management, customer communication and cross-functional leadership skills are required, along with familiarity with Linux environments.
Linux
Project Engineering Management, Principal Engineer
Mississauga, ONSynopsys
10+ ansCandidates need an engineering degree or equivalent experience, 10+ years of customer-facing project management, and familiarity with mixed-signal IP, SoC or ASIC development. Strong communication, MS Project, Jira, UNIX/Linux and quality management system knowledge are also required.
MS Project, Jira, UNIX, Linux
Hardware Validation Engineer, Sr Staff
Nepean, ONSynopsys
6+ ansCandidates need 6-8+ years of high-speed hardware design and validation experience and expert Cadence Allegro skills. They also need strong signal integrity knowledge, bench debugging experience and familiarity with JTAG, I2C, SPI and UART interfaces.
Cadence Allegro, logic analyzer, oscilloscope, VNA, spectrum analyzer, protocol analyzer
Product Management , Staff
Vancouver, BCSynopsys
5+ ansCandidates need a technical degree or equivalent experience and at least five years of product management in photonics, optics or simulation software. They should understand photonic design workflows and simulation methods such as FDTD, and have experience with tools like OptoCompiler or Lumerical.
OptoCompiler, Lumerical
Sr Staff Package Design Engineer
Nepean, ONSynopsys
10+ ansCandidates need 10+ years of semiconductor package design or electrical modeling experience and a bachelor's degree in electrical or electronics engineering. They must have strong skills in circuit theory, 3D EM modeling in Ansys HFSS, and clear communication in English.
Ansys HFSS, EDA tools, Windows, Linux
Sr Staff PCB Design Engineer
Markham, ONSynopsys
10+ ansCandidates need 10+ years of high-speed PCB design or signal integrity experience and strong circuit and transmission line theory. They also need hands-on 3D electromagnetic modelling experience with Ansys HFSS or similar tools, plus a Bachelor's degree in electrical or electronics engineering.
Ansys HFSS, PCB layout tools, Windows, Linux
ASIC Digital Verification, Sr. Manager
Mississauga, ONSynopsys
15+ ansCandidates need a BS or MS in EE, EC or VLSI with 15+ years of IP or SoC verification experience, and strong team leadership. They must know Verilog, SystemVerilog and UVM, and Perl or Python automation. PCIe and Ethernet knowledge is an asset.
Verilog, SystemVerilog, UVM, Perl, Python