Design Engineer
Markham, ONContrat
D
Dexian
Candidates need strong ASIC synthesis and static timing analysis experience, hands-on use of EDA tools such as Design Compiler and PrimeTime, and Verilog or SystemVerilog skills. Experience with UPF/CPF, advanced process nodes and scripting for automation is a strong asset.
Synopsys Design Compiler, PrimeTime, PrimePower, Power Artist, Verilog, SystemVerilog