FPGA Designer
Ottawa, ONTemps plein
LO
Lumentum Ottawa ULC
Candidates need experience designing ASIC or FPGA logic in Verilog or SystemVerilog, including synthesis, timing and clock domain crossing, plus AMD (Xilinx) or Altera tools. Strong debugging skills and clear communication are required.
Xilinx, Altera, Verilog, SystemVerilog