Senior Staff ML Compiler and Performance Engineer
Markham, ONTalentlab
4+ ansCandidates need a bachelor's degree in a related field and 4+ years of engineering experience. Strong algorithm, performance analysis, C++, Python and communication skills are essential.
C++, Python, PyTorch, TensorFlow, ONNX, git
Program Manager – High-Speed SerDes IP
Toronto, ONTalentlab
8+ ansCandidates need 8+ years in the semiconductor industry with a focus on high-speed SerDes IP, a Bachelor's in Electrical Engineering or a related field, and a solid understanding of IP deliverables and integration. PMP certification and ASIC or protocol knowledge are assets.
Jira, MS Office
Staff Design Verification Engineer
Toronto, ONTalentlab
9+ ansCandidates need a Bachelor's or Master's in computer science, electrical engineering or a related field, plus at least 9 years of ASIC design verification experience. Strong SystemVerilog and UVM skills and advanced debugging are required.
SystemVerilog, UVM, EDA tools
Senior Design Verification Engineer
Toronto, ONTalentlab
3+ ansTalentlab needs candidates with 3 to 8 years of design verification experience and strong SystemVerilog and UVM skills. Experience with SerDes, DSP or mixed-signal designs is needed, and Ethernet and PCIe knowledge is a strong plus.
SystemVerilog, UVM, Python, Perl, C/C++, GNU Make
Staff Physical Design Engineer
Toronto, ONTalentlab
5+ ansCandidates need 5+ years of physical design experience on digital ASICs, including advanced nodes like TSMC N5, N4P or N3. They must know industry EDA tools, PnR, timing analysis and physical verification, and be strong in TCL, Python or Perl.
Synopsys ICC2, Cadence Innovus, Calibre, PrimeTime, RedHawk, TCL
Analog IC Design Engineer
Toronto, ONTalentlab
5+ ansCandidates need an MSc or PhD in electrical engineering or a related field and 5+ years of analog IC design experience, preferably silicon-proven. They need hands-on advanced CMOS experience, SPICE and Verilog-A simulation skills, and EDA tool proficiency.
SPICE, Verilog-A, EDA tools