Staff Design Verification Engineer
Toronto, ONTalentlab
9+ ansCandidates need a Bachelor's or Master's in computer science, electrical engineering or a related field, plus at least 9 years of ASIC design verification experience. Strong SystemVerilog and UVM skills and advanced debugging are required.
SystemVerilog, UVM, EDA tools
Analog IC Design Engineer
Toronto, ONTalentlab
5+ ansCandidates need an MSc or PhD in electrical engineering or a related field and 5+ years of analog IC design experience, preferably silicon-proven. They need hands-on advanced CMOS experience, SPICE and Verilog-A simulation skills, and EDA tool proficiency.
SPICE, Verilog-A, EDA tools
Staff ASIC Design Engineer – AI/ML Hardware IP
Toronto, ONTalentlab
5+ ansCandidates need at least 5 years of hands-on ASIC design experience and strong skills in Verilog, SystemVerilog, and logic synthesis. A degree in electrical or computer engineering is required, and candidates must be legally authorized to work on-site in Canada.
Verilog, SystemVerilog, Design Compiler, PrimeTime, Formality, Spyglass
Lead / Principal System Verification Engineer – Optical Networking
Ottawa, ONTalentlab
5+ ansCandidates need at least 5 years of system verification or validation experience in telecom or networking, hands-on DWDM or optical transport experience, and strong Python skills. A degree in electrical engineering, computer science or a related field is required.
Python, Jenkins, GitLab, CLI, gRPC, optical spectrum analyzer