Senior Design Verification Engineer
Toronto, ONT
Talentlab
3+ ansTalentlab needs candidates with 3 to 8 years of design verification experience and strong SystemVerilog and UVM skills. Experience with SerDes, DSP or mixed-signal designs is needed, and Ethernet and PCIe knowledge is a strong plus.
SystemVerilog, UVM, Python, Perl, C/C++, GNU Make
Staff Firmware Engineer — CPU Telemetry & Drivers
Markham, ONT
Talentlab
Candidates need strong embedded or firmware development experience, advanced C or C++ skills, and a solid understanding of CPU and SoC architecture. Experience with performance counters, telemetry or diagnostics, and Linux knowledge, are valued, along with a Bachelor's or Master's degree in a related engineering or computer science field.
C, C++, Linux