Senior Design Verification Engineer
Toronto, ONT
Talentlab
3+ ansTalentlab needs candidates with 3 to 8 years of design verification experience and strong SystemVerilog and UVM skills. Experience with SerDes, DSP or mixed-signal designs is needed, and Ethernet and PCIe knowledge is a strong plus.
SystemVerilog, UVM, Python, Perl, C/C++, GNU Make