Emplois “CXL IP” au Canada

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• 33m

  Staff PCIe Verification Engineer

  Toronto, ON

  A

  ARM

  7+ ansArm needs candidates with a Bachelor's or Master's degree in computer science or electrical or computer engineering and 7+ years of PCIe or CXL verification experience. They must have strong Verilog and UVM skills, simulation and emulation experience, and knowledge of formal methods.

  SystemVerilog, Verilog, UVM, PCIe IP, CXL IP, Emulation platforms

  33m

  Senior PCIe Design Engineer

  Toronto, ON

  A

  ARM

  5+ ansArm needs candidates with a Bachelor's or Master's degree in a related engineering or computer science field and 5+ years of SoC or compute subsystem design experience. Candidates need Verilog, PCIe, CXL or Ethernet integration experience and scripting skills in Perl or Python.

  Verilog HDL, Perl, Python

  33m

  Senior PCIe Verification Engineer

  Toronto, ON

  A

  ARM

  4+ ansCandidates need a Bachelor's or Master's degree in a related engineering or computer science field and 4+ years of PCIe or CXL verification experience. Strong skills in Verilog, UVM, debugging and simulation or emulation platforms are required.

  SystemVerilog, Verilog, UVM, Debuggers, Simulation platforms, Emulation platforms

  33m

  Staff PCIe Design Engineer

  Toronto, ON

  A

  ARM

  10+ ansCandidates need a Bachelor's or Master's degree in computer science or electrical or computer engineering, 10+ years designing complex SoCs or compute subsystems, and strong Verilog and digital design skills. Experience with PCIe, CXL, UCIe or Ethernet subsystems and static design checks is required.

  Verilog HDL, Perl, Python

• 10j

  FY27 Intern - Soft IP ASIC Engineering Internship - Canada (12 or 16 months)

  Ottawa, ON

  Sur placeStage

  

  Qualcomm Canada ULC

  1+ ansQualcomm Canada needs candidates studying toward a bachelor's degree in electrical, computer or engineering science, or computer science. They need scripting experience in Python, Perl, TCL or Unix/Linux shell, plus source control experience with SVN, CVS or RCS.

  Verilog, SystemVerilog, UVM, SVN, CVS, RCS

  10j

  FY27 Intern - Softip Engineering Co-Op - Canada (4 months)

  Ottawa, ON

  Sur placeStage

  

  Qualcomm Canada ULC

  1+ ansCandidates need to be enrolled in a bachelor's or master's program in electrical, computer or related engineering, with scripting experience in Python, Perl, TCL or Unix/Linux shell and experience with source code revision systems.

  Verilog, SystemVerilog, UVM, VHDL, SVN, CVS

  10j

  FY27 Intern - Firmware/Embedded Software Engineering Internship - Canada (12 or 16 months)

  Toronto, ON

  Sur placeStage

  

  Qualcomm Canada ULC

  1+ ansCandidates need to be enrolled in a bachelor's degree in electrical or computer engineering, engineering science or computer science, with at least one year of academic programming experience in C, C++ or Python. Strong debugging, problem-solving and teamwork skills are needed, and availability must match the 12- or 16-month internship dates.

  Git, Linux, FPGA, Verilog, SystemVerilog, GitHub Actions

  1 mois

  Firmware Engineer, Principal

  Toronto, ON

  Sur place

  

  Qualcomm Canada ULC

  8+ ansCandidates need an engineering or computer science degree plus 8+ years of software engineering experience, or a master's with 7+ years. They also need 4+ years coding in C, C++, Java or Python, strong embedded firmware and lab debug skills, and team leadership experience.

  Git, Python, RISC-V

  1 mois

  Firmware Engineer – SerDes PHY (all levels)

  Toronto, ON

  Sur place

  

  Qualcomm Canada ULC

  6+ ansCandidates need an engineering or computer science degree and 4 to 6+ years of software engineering experience, depending on degree level. They also need at least 3 years of programming experience in languages such as C, C++, Java or Python.

  JTAG debuggers, git, Verilog, SystemVerilog

• 14j

  Pre-Si Validation Engineer

  Toronto, ON

  Temps plein

  

  Intel Corporation

  6+ ansCandidates need a Bachelor's degree in electrical or computer engineering, 6+ years with formal verification tools and methods, SystemVerilog, and CPU architecture including cache coherence and CXL. Strong problem-solving and communication skills are expected.

  formal verification tools

• 18j

  Physical Design Engineering Director

  Toronto, ON

  

  Astera Labs: Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions.

  15+ ans5+ gestionCandidates need a bachelor's degree in an electrical or computer engineering field, with 15+ years of physical design experience on advanced nodes and 5+ years leading teams. Hands-on skill with Cadence Innovus or Synopsys tools and scripting in Tcl, Python or Perl is required.

  Cadence Innovus, Synopsys Fusion Compiler, ICC2, Tcl, Python, Perl

• 27j

  Silicon Design Engineer - Technical Lead

  Markham, ON

  Temps plein

  AI

  AMD, Inc.

  AMD needs candidates with experience in I/O protocols such as USB, PCIe and CXL, plus micro-architecture and RTL design for multi-clock, high-frequency, low-power designs. A master's or bachelor's in electrical engineering or equivalent is preferred.

  Python, Perl

  27j

  RTL Design Engineer

  Markham, ON

  Temps plein

  AI

  AMD, Inc.

  Candidates need experience with I/O protocols such as USB, PCIe and CXL, plus RTL design for multi-clock, high-frequency, low-power designs. A bachelor's or master's degree in electrical engineering or equivalent is preferred.

  Python, Perl

  27j

  Design Verification Lead

  Markham, ON

  Temps plein

  AI

  AMD, Inc.

  Candidates need a bachelor's or master's degree in electrical or computer engineering, computer science or a related field, plus UVM and SystemVerilog experience and knowledge of high-speed protocols such as PCIe, CXL or Ethernet. Scripting in Python or Perl and technical leadership skills are also needed.

  SystemVerilog, Verilog, UVM, Python, Perl

• 27j

  Digital Design Engineer Intern (Toronto)

  Toronto, ON

  AL

  Astera Labs Early Career - North America 2027

  Candidates need to be pursuing a bachelor's or master's degree in electrical, computer engineering, computer science or a related field. They need digital logic or RTL coursework or project experience, programming skills in Verilog, SystemVerilog, C/C++ or Python, and familiarity with Linux and Git.

  Verilog, SystemVerilog, Linux, Git, Python, Tcl

  27j

  Design Verification Engineer Intern (Toronto)

  Toronto, ON

  AL

  Astera Labs Early Career - North America 2027

  Candidates need to be pursuing a bachelor's or master's degree in electrical, computer engineering or computer science. They need coding skills in SystemVerilog, C/C++ or Python, Linux and Git familiarity, and strong debugging ability.

  VCS, Verdi, DVE

• 28j

  Design Verification Lead

  Markham, ON

  Temps plein

  AM

  Advanced Micro Devices, Inc

  Candidates need a Bachelor's or Master's degree in an electrical, computer or related engineering field, strong UVM and SystemVerilog skills, and experience verifying high-speed protocols such as PCIe, CXL or Ethernet. Technical leadership, mentoring and scripting in Python or Perl are preferred.

  SystemVerilog, Verilog, UVM, Python, Perl

  1 mois

  Silicon Design Engineer - Technical Lead

  Markham, ON

  Temps plein

  AM

  Advanced Micro Devices, Inc

  Advanced Micro Devices needs candidates with experience in I/O protocols such as USB, PCIe and CXL, plus micro-architecture and RTL design for high-speed, low-power digital blocks. A master's or bachelor's degree in electrical engineering or equivalent is preferred.

  Python, Perl

  1 mois

  RTL Design Engineer

  Markham, ON

  Temps plein

  AM

  Advanced Micro Devices, Inc

  Candidates need experience with I/O protocols such as USB, PCIe and CXL, plus RTL design for multi-clock, high-frequency, low-power designs. Strong analytical, communication and teamwork skills are expected, along with scripting in Python or Perl.

  RTL, DFT, Firmware, Analytical skills, Problem solving, Attention to detail

• 1 mois

  Senior SoC Architect (f/m/d)

  Toronto, ON

  TélétravailTemps plein

  

  Black Semiconductor GmbH

  7+ ansCandidates need 7 to 10 years of SoC or product architecture experience, including taking a product from market requirements to a detailed design. Deep high-speed I/O expertise (SerDes, UCIe, PCIe, Ethernet) and experience with on-chip interconnects are essential.

  Python, C++

• 1 mois

  Principal SI/PI Engineer - 18619

  Mississauga, ON

  S

  Synopsys

  12+ ansCandidates need a bachelor's degree (master's or PhD preferred) in electrical engineering and 12+ years of high-speed SI/PI experience on SerDes links. They also need strong skills in simulation tools, lab measurement and scripting, plus proven technical leadership.

  HSPICE, Keysight ADS, SystemVue, Ansys HFSS, SIwave, AEDT

• 1 mois

  Design Verification Engineer - technical lead, Annapurna Labs

  Toronto, ON

  Temps plein

  AD

  Amazon Development Centre Canada ULC

  8+ ansCandidates need a bachelor's degree in electrical engineering or a related field and 8+ years of constrained-random verification experience (such as UVM), including testbench development. Experience across IP, SoC and full-system verification, plus formal, emulation or scripting skills, is highly desired.

  UVM, formal verification tools, emulation platforms, Python, Perl

• 1 mois

  SMTS Logic Design

  Montréal, QC

  

  Rambus: As an industry pioneer with over 30 years experience, Rambus is a premier provider of chips & silicon IP.

  8+ ansCandidates need a BS, MS or PhD in electrical or computer engineering, 8+ years of ASIC/SoC logic design experience, and expert SystemVerilog skills. Experience with synthesis, timing closure and PCIe Gen5/Gen6/Gen7 is preferred.

  SystemVerilog, Synopsys Design Compiler, Synopsys Fusion Compiler, Cadence Genus, SpyGlass, Questa

• 1 mois

  Technical Staff Engineer - Design

  Burnaby, BC

  107k–226k $/anTemps plein

  MS

  MCHP Semiconductor Canada ULC

  12+ ansCandidates need a B.S. in electrical engineering with 12+ years of related experience, hands-on pad ring and bump map work for advanced SoC designs, and knowledge of IO standards such as SerDes, DDR, PCIe and CXL. Scripting skills in Tcl or Python are required.

  Orbit IO, ISP, Tcl, Python, Verilog, SVN

12 entreprises