FY27 Intern - Display IP FPGA Emulation Intern - Canada (4 months)
Markham, ONQualcomm Canada ULC
1+ ansCandidates need to be in study toward a bachelor's degree in computer engineering, engineering science, computer science or a related field, with at least one year of academic programming experience. Knowledge of RTL, Verilog or SystemVerilog, digital design and Linux is required, plus teamwork and communication skills.
FPGA, Verilog, Linux, Perl, Python, TCL
GPU Design Verification Engineer
Markham, ONQualcomm Canada ULC
2+ ansCandidates need a relevant engineering or computer science degree plus years of hardware or software experience, depending on degree level. They need SystemVerilog, UVM, C/C++ and verification skills such as test planning, simulation and debug.
UVM, Veloce, Palladium, Zebu, FPGA, Python
Verification Engineer (Engineer–Senior Level)
Toronto, ONQualcomm Canada ULC
2+ ansCandidates need a bachelor's degree in science or engineering with 2+ years of ASIC design or verification experience, or a master's with 1+ year, or a PhD. Strong SystemVerilog and UVM skills, constrained random verification experience and clear communication are required.
SystemVerilog, UVM, Python, Perl, C/C++, GNU Make
Sr ASIC Design Verification Engineer, Low Power AI
Markham, ONQualcomm Canada ULC
2+ ansQualcomm Canada ULC needs candidates with a bachelor's, master's or PhD and 2 to 4+ years of ASIC work, depending on degree. Expert skill in Verilog, SystemVerilog, UVM and C, plus a deep understanding of ASIC/VLSI concepts, is required.
SystemVerilog, UVM, Verilog, VHDL, SystemC, Perl
FY27 Intern - Display IP Engineering Internship - Canada (16 months)
Markham, ONQualcomm Canada ULC
1+ ansCandidates need to be enrolled in a bachelor's program in electrical, computer or engineering science, or a related field, with a graduation date of November 2028 or later. They need programming experience in C, C++ or Python, knowledge of RTL, Verilog or SystemVerilog and digital design, and good communication and teamwork skills.
Verilog, VHDL, Perl, Python, TCL, GNU Make
Staff ASIC Verification Engineer, Low Power AI
Markham, ONQualcomm Canada ULC
4+ ansQualcomm Canada ULC needs candidates with a relevant degree and 4+ years of ASIC work (3+ with a master's, 2+ with a PhD). Expert knowledge of Verilog, VHDL and SystemVerilog UVM is required, plus solid C skills.
SystemVerilog, UVM, Verilog, VHDL, SystemC, Perl
Digital Design Verification Engineer, Staff
Toronto, ONQualcomm Canada ULC
4+ ansCandidates need a bachelor's degree in a science or engineering field with 4+ years of ASIC design or verification experience, or an equivalent master's or PhD with less experience. Strong SystemVerilog, UVM and scripting skills and proven leadership and communication are required.
Verilog, SystemVerilog, UVM, Python, Perl, C/C++