Senior ASIC Design Verification Technical Lead
Vancouver, BCTemps plein
ST
Scaledge Technology
7+ ansCandidates need an engineering bachelor's degree, 7+ years in ASIC, SoC or subsystem verification, and experience leading verification teams. Hands-on SystemVerilog, UVM, RTL debugging and coverage closure, plus a protocol such as Ethernet or AXI, are required.
SystemVerilog, UVM, Synopsys VCS, Verdi, QuestaSim, ModelSim