FPGA Digital Design Engineer (6+ month Contract)
Toronto, ONKepler Communications
5+ ansCandidates need a bachelor's degree in computer or electrical engineering, 5+ years of FPGA/RTL design experience, and skill in Verilog, SystemVerilog or VHDL. They also need Xilinx Zynq or UltraScale experience, timing and clock domain crossing knowledge, and scripting skills.
Vivado, Quartus, ModelSim, Python, Tcl
FPGA Digital Design Engineer
Toronto, ONKepler Communications
5+ ansCandidates need a bachelor's degree in computer or electrical engineering and 5+ years of FPGA/RTL design experience. They must know Verilog, SystemVerilog or VHDL, Xilinx Zynq and UltraScale devices, clock domain crossing and timing closure, and scripting in Python or Tcl.
Vivado, Quartus, ModelSim, Questa Sim, Riviera-Pro, Python