Analog Engineer, Staff
Toronto, ONQualcomm Canada ULC
4+ ansCandidates need a bachelor's, master's or PhD in electrical engineering with analog or mixed-signal CMOS design experience and several years of ASIC design or verification work. Experience with circuit design tools, transistor-level design, layout optimization and silicon-proven analog blocks is required.
Cadence ADE, MATLAB, SPICE, Verilog-A, Verilog, VHDL
Staff CPU/NPU Architecture RTL Design Engineer
Markham, ONQualcomm Canada ULC
2+ ansCandidates need a bachelor's, master's or PhD in a related field, with 4+, 3+ or 2+ years of ASIC design experience respectively. They also need knowledge of CPU or AI processor micro-architecture, RTL design and power management.
RTL, Scheduling, Recruitment
DSP Application Engineer, Staff
Ottawa, ONQualcomm Canada ULC
5+ ansCandidates need a BS or MS in an technical field and 5 to 7 years of experience in semiconductors, networking or optical communications. They need knowledge of PAM4 signalling, SerDes, equalization and Ethernet, plus skill with high-speed test equipment and Python or MATLAB.
Oscilloscope, BERT, VNA, Python, MATLAB
Hardware Design Engineer – Application Engineering, Staff
Ottawa, ONQualcomm Canada ULC
4+ ansCandidates need a bachelor's degree in an engineering or computer science field with 4+ years of hardware engineering experience, or a master's with 3+ years, or a PhD with 2+ years. Strong high-speed PCB, SerDes and PAM4 knowledge, lab bring-up skills and signal and power integrity expertise are required.
HFSS, Laboratory test equipment, Schematic capture tools, PCB layout tools
Cross-Functional Engineer, Staff
Toronto, ON +1Qualcomm Canada ULC
4+ ansCandidates need a bachelor's, master's or PhD in Electrical Engineering with analog or mixed-signal chip design experience and several years of ASIC design or verification work. They also need strong high-speed SerDes knowledge, SystemVerilog and EDA tool skills.
Cadence, SPICE, MATLAB, Verilog, VHDL, SystemVerilog
Analog Engineer, Principal
Toronto, ONQualcomm Canada ULC
8+ ansCandidates need a Master's or PhD in electrical engineering (or a Bachelor's with 2+ years of analog or mixed-signal design), plus 8+ years of ASIC design or related work and silicon-proven analog circuit experience in advanced CMOS. Strong skills in Cadence, SPICE, MATLAB or Verilog-A are expected.
Cadence ADE, MATLAB, SPICE, Verilog-A
Sr ASIC Design Verification Engineer, Low Power AI
Markham, ONQualcomm Canada ULC
2+ ansQualcomm Canada ULC needs candidates with a bachelor's, master's or PhD and 2 to 4+ years of ASIC work, depending on degree. Expert skill in Verilog, SystemVerilog, UVM and C, plus a deep understanding of ASIC/VLSI concepts, is required.
SystemVerilog, UVM, Verilog, VHDL, SystemC, Perl