ASIC Physical Design Engineer - DFT, Senior
Télétravail au CanadaTélétravailTemps plein
Positron AI
8+ ansPositron AI needs 8+ years of ASIC development with several production tapeouts, deep DFT experience, and hands-on Siemens Tessent. Candidates also need Verilog/SystemVerilog RTL skills, synthesis and gate-level verification, and scripting in Python, Tcl or Perl.
Siemens Tessent, Verilog, SystemVerilog, Python, Tcl, Perl
ASIC Design Engineer, Senior
Télétravail au CanadaTélétravailTemps plein
Positron AI
8+ ansCandidates need a BS or MS in electrical or computer engineering with 8+ years of ASIC or SoC RTL design experience. They need deep SystemVerilog skills, front-end EDA tool expertise, and hands-on work with at least three of HBM/DDR, PCIe/CXL, AMBA AXI/ACE/CHI, cache hierarchies, or high-throughput datapaths.
SystemVerilog, Python, Tcl, Make, UVM, cocotb