ASIC Engineer Intern
Ottawa, ON25,50–35 $/hTemps plein
CC
Ciena Canada ULC
Candidates need programming experience in Java, Python, TCL, Skill/Ocean or SystemVerilog, and familiarity with Linux. Experience with ASIC or FPGA work, debugging skills and Agile, JIRA, Confluence or Git are assets.
SystemVerilog, UVM, Python, TCL, Skill/Ocean, Java
Senior Manager, Lifecycle Management & Reliability
Ottawa, ON154k–253k $/anTemps plein
CC
Ciena Canada ULC
10+ ans3+ gestionCandidates need a bachelor's degree in an engineering discipline and 10+ years of hardware engineering experience in telecom, networking or optical systems, including 3+ years leading teams. They must have strong skills in reliability, qualification, failure analysis and cross-functional leadership.
Agile PLM, Jira, Confluence