SoC Design Lead, Microarchitecture and Design Methodology
Markham, ONAdvanced Micro Devices, Inc
AMD needs candidates with a strong foundation in digital design, computer architecture, static timing analysis and power optimization. Strong written and verbal communication, analytical skills and a degree in computer, electrical engineering or a related field are preferred.
Verilog, SystemVerilog, UVM
Silicon Design Engineer - Technical Lead
Markham, ONAdvanced Micro Devices, Inc
Advanced Micro Devices needs candidates with experience in I/O protocols such as USB, PCIe and CXL, plus micro-architecture and RTL design for high-speed, low-power digital blocks. A master's or bachelor's degree in electrical engineering or equivalent is preferred.
Python, Perl
Physical Design Engineer
Markham, ONAdvanced Micro Devices, Inc
8+ ansCandidates need a bachelor's, master's or PhD in electrical, electronics or computer engineering, with 8, 4 or 2 years of physical design experience respectively. They need expertise in block-level place and route, timing closure, physical verification and power, performance and area optimization, plus hands-on debugging of EDA tools from Synopsys, Cadence and Siemens.
Synopsys ICC2, Cadence Innovus, Synopsys PrimeTime, Spyglass, RedHawk, Calibre
Static Timing Analysis / Full Chip Timing Engineer
Markham, ONAdvanced Micro Devices, Inc
Advanced Micro Devices needs a BS, MS or PhD in electrical or computer engineering or a related field. Full-chip timing experience is preferred.
SDC
RTL Design Engineer
Markham, ONAdvanced Micro Devices, Inc
Candidates need experience with I/O protocols such as USB, PCIe and CXL, plus RTL design for multi-clock, high-frequency, low-power designs. Strong analytical, communication and teamwork skills are expected, along with scripting in Python or Perl.
RTL, DFT, Firmware, Analytical skills, Problem solving, Attention to detail
Lead Physical Design Engineer, Place & Route
Markham, ONAdvanced Micro Devices, Inc
Candidates need deep hands-on place-and-route experience on complex chip designs, including timing closure and physical verification. Experience with Synopsys Fusion Compiler, Cadence and Siemens EDA tools, plus TCL, Perl or Shell scripting, is preferred, and a Bachelor's or Master's degree in electrical or computer engineering is preferred.
Synopsys Fusion Compiler, Cadence, Siemens EDA, TCL, Perl, Shell
STA/Constraints Engineer
Vancouver, BCAdvanced Micro Devices, Inc
Candidates need industry experience in static timing analysis, constraints and timing signoff, plus expert use of Synopsys PrimeTime and GCA. Scripting in Perl, TCL, Shell or Python, and a degree in microelectronics or a related field, are preferred.
GCA, ICC2, Verilog, Perl, TCL, Python
SoC Physical Design Implementation Lead
Markham, ONAdvanced Micro Devices, Inc
Advanced Micro Devices needs seasoned physical design experience on advanced nodes, with hands-on place and route, timing and sign-off skills. Candidates should know Synopsys, Cadence and Siemens tools and scripting in Tcl, Perl or Shell; a Bachelor's or Master's in electrical or computer engineering is preferred.
Synopsys tools, Cadence tools